Friday
   
12:00 Registration open at Town Hall
13:00 Room open
13:15 Conference Welcome - Video
13:30 An Open Source PDVL Framework - Tobias Strauch - Slides - Video
14:00 Kactus2: Update on the open source IP-XACT tool - Esko Pekkarinen - Slides - Video
14:30 Progress of the OpTiMSoC project - Stefan Wallentowitz - Video
15:00 UVVM – Universal VHDL Verification Methodology - Espen Tallaksen - Slides - Video
15:45 Break
16:30 An overview of recent RISC-V Foundation activities - Alex Bradbury - Video
17:00 Open-source EDA community building - Kunal Promode Ghosh - Video
17:30 Software to hardware portability - Steven van der Vlugt
18:00 Pints and Pudding time
   
  Saturday
   
08:00 Registration open at Town Hall, coffee served
09:00 FOSSi Foundation update - FOSSi Foundation - Slides - Video
09:30 LibreCores - your source for free and open digital hardware - Philipp Wagner - Slides - Video
10:00 State of LibreCores CI - Stefan Wallentowitz and Oleg Nenashev - Slides - Video
10:30 Poster presentations + Break
11:00 The CERN OHL v2 and copyleft licences for HDL - Andrew Katz - Video
11:30 AutoFPGA: An FPGA Component Aggregator - Dan Gisselquist - Video
12:00 chips4makers - Staf Verhaegen - Slides - Video
12:30 Lunch
14:00 End-to-end formal ISA verification of RISC-V processors with riscv-formal - Clifford Wolf - Slides - Video
14:30 Open Circuit Design - R. Timothy Edwards - Slides - Video
15:00 lowRISC project update - Alex Bradbury - Video
15:30 Sequential Consistency on lowRISC - Mahircan Gul - Slides - Video
15:50 Lightning talks: ZipCPU update - Slides - Video, What the Heck is System Hyper Pipelining? - Slide Video, FuseSoc - Video, myStorm - Video
16:00 Break
16:30 Open SoC Debug: Reusable debug and trace components with added value - Philipp Wagner - Slides - Video
17:00 Experience report: Bringing up cycle-accurate models of RISC-V cores - Graham Markall - Video
17:30 RFC: Is open source from Venus and commercial from Mars? - Staf Verhaegen - Slides - Video
18:00 Pre-dinner break, mingle
19:00 Dinner
   
  Sunday
   
08:30 Registration open at Town Hall, coffee served
09:30 EDSAC Museum on FPGA - Hatim Kanchwala - Slides - Video
10:00 Chip Hack EDSAC 2017 - Mary Bennett, Peter Bennett, Dan Gorringe - Video
10:30 Break
11:00 PULP: an Open Source Parallel Computing Platform - Davide Rossi - Slides - Video
11:30 Your Many-Core Future: Practical Applications of Open Hardware - Michael Brodeur - Video
12:00 Lunch
13:00 efabless: Reinventing Hardware Innovation - R. Timothy Edwards - Slides - Video
13:30 SCR1: an open-source MCU-class RISC-V core - Ekaterina Berezina, Vasily Varaksin - Slides - Video
14:30 Post-conference mingle
15:00 Doors close. See you next year!