Friday
   
12:00 Registration open at Town Hall
13:00 Room open
13:15 Conference Welcome
13:30 An Open Source PDVL Framework - Tobias Strauch (20m + 10m Q&A)
14:00 Kactus2: Update on the open source IP-XACT tool - Esko Pekkarinen (15+5)
14:30 Progress of the OpTiMSoC project - Stefan Wallentowitz (10+5)
15:00 UVVM – Universal VHDL Verification Methodology - Espen Tallaksen (20+10)
15:45 Break
16:30 An overview of recent RISC-V Foundation activities - Alex Bradbury (15+5)
17:00 Open-source EDA community building - Kunal Promode Ghosh (20+10)
17:30 Software to hardware portability - Steven van der Vlugt (20+10)
18:00 Pints and Pudding time
   
  Saturday
   
08:00 Registration open at Town Hall, coffee served
09:00 FOSSi Foundation update - FOSSi Foundation (15+10)
09:30 LibreCores - your source for free and open digital hardware - Philipp Wagner (15+5)
10:00 State of LibreCores CI - Stefan Wallentowitz and Oleg Nenashev (20+10)
10:30 Poster presentations + Break
11:00 The CERN OHL v2 and copyleft licences for HDL - Andrew Katz (20+10)
11:30 AutoFPGA: An FPGA Component Aggregator - Dan Gisselquist (20+10)
12:00 Chips4Makers - Staf Verhaegen (15+5)
12:30 Lunch
14:00 End-to-end formal ISA verification of RISC-V processors with riscv-formal - Clifford Wolf (20+10)
14:30 Open Circuit Design - R. Timothy Edwards (15+5)
15:00 lowRISC project update - Alex Bradbury (20+10)
15:30 Sequential Consistency on lowRISC - Mahircan Gul (10+5)
15:50 Lightning talks - ZipCPU update, What the Heck is System Hyper Pipelining?
16:00 Break
16:30 Open SoC Debug: Reusable debug and trace components with added value - Philipp Wagner (15+5)
17:00 Experience report: Bringing up cycle-accurate models of RISC-V cores - Graham Markall (15+5)
17:30 RFC: Is open source from Venus and commercial from Mars? - Staf Verhaegen (15+5)
18:00 Pre-dinner break, mingle
19:00 Dinner
   
  Sunday
   
08:30 Registration open at Town Hall, coffee served
09:30 EDSAC Museum on FPGA - Hatim Kanchwala (20+10)
10:00 Chip Hack EDSAC 2017 - Mary Bennett, Peter Bennett, Dan Gorringe (15+5)
10:30 Break
11:00 PULP: an Open Source Parallel Computing Platform - Davide Rossi (20+10)
11:30 Your Many-Core Future: Practical Applications of Open Hardware - Michael Brodeur (20+10)
12:00 Lunch
13:00 efabless: Reinventing Hardware Innovation - R. Timothy Edwards (15+5)
13:30 SCR1: an open-source MCU-class RISC-V core - Ekaterina Berezina, Vasily Varaksin (10+5)
14:00 TBD
14:30 Post-conference mingle
15:00 Doors close. See you next year!