ORConf

The open source digital design conference


Registration - Presentations - Venue - Sponsors


ORConf 2018 will be held from September 21st to 23rd in Gdansk, Poland, at the Gdansk University of Technology

Sign up to the orconf-announce mailing list for further details as they're announced.

About

ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space.

We invite anyone with an interest in the field to join us and also consider a presentation, big or small, on your experience as a developer or a user of open source digital design projects.

ORConf remains to be free to attend thanks to each year's sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!

Previous editions: 2017 - 2016 - 2015 - 2014 - 2013 - 2012

Registration

ORConf is free to attend but you must register.

Register to attend here

Presentation Submissions

We encourage anybody involved in the open source semiconductor engineering space to come along and give share your work or experience. Presentations slots as short as 3 minute lightning-talks up to 30 minute talks with Q and A are available.

So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.

Submit your presentation proposal here

Schedule

The conference will run from about 12:30PM on Friday the 21st until around 3PM on the Sunday, permitting people to travel on the first and last day of the event and not miss any sessions.

The running order will be determined closer to the event.

Presentations

Below are some of the presentation submissions we've accepted so far.

Verilator 4.0 - Open Simulation Goes Multithreaded

The primary author of Verilator, the open source high-speed Verilog simulator, announces fresh for this meeting Verilator 4.0 with multithreading, and how you can get your designs' the fast(est), free simulation.

Presenter: Wilson Snyder

Wilson is one of the primary authors of Verilator and maintains Veripool.org.

Symbiotic EDA

nextpnr is a retargetable FOSS FPGA place-and-route tool that is replacing arachne-pnr as place-and-route tool in the IceStorm open source iCE40 flow. It is retargetable, meaning it can be ported to other FPGA architectures easily, uses timing-driven algorithms, provides a python scripting API, supports complex placement and floorplanning constraints, and has a nice GUI. Python and GUI support are optional, which may be useful when deploying nextpnr on an embedded platform.

This presentation covers nextpnr from a user perspective, but also gives a few pointers for how to port nextpnr to new FPGA architectures.

Presenter: Clifford Wolf

Clifford is the lead engineer of the nextpnr project. He is also is the author of riscv-formal, Yosys, and SymbiYosys.

An update on SymbiFlow - a multiplatform FPGA project

SymbiFlow aims to be the "gcc of FPGAs", a fully open source project which supports multiple FPGAs from many different manufactures. It is currently targeting the Lattice iCE40, Lattice ECP5 and Xilinx 7 series FPGAs.

This presentation will give you an update on the current status of the project. What currently works, the future roadmap and how you can help with the project.

Presenter: Tim 'mithro' Ansell

Tim is the founder of TimVideos and is currently heavily involved with the development of the SymbiFlow project.

Unpacking Xilinx 7-Series Bitstreams

Project X-Ray follows in the footsteps of Project Icestorm by documenting the low-level details of Xilinx 7-Series FPGAs. This family of devices is considerably more featureful and, correspondingly, more complicated than previously documented families. Through perseverance and a little luck, enough has been learned to configure logic cells and rewrite bitstreams.

This talk will cover what is known about the bitstream format, programming process, device architecture, and the current state of tools and their capabilities.

Presenter: Rick Altherr

Rick is a software engineer with experience ranging from ASIC debugging to UX. Before leaving Google, he led teams in the development of computing equipment for Google's data centers and worked across the computing industry to found OpenBMC, an open-source firmware stack for server management, under the Linux Foundation. Outside his day job, Rick develops Gaffe, an experimental framework for rapidly building tools for logic design, and designs electronics for race car engine control and tuning.

OpenRISC Update

Since the last ORConf I attended I have made lots of progress on getting the OpenRISC toolchain and Linux support in shape and upstreamed. I will talk about recent developments and what is on the roadmap for OpenRISC.

Presenter: Stafford Horne

Stafford has been involved in Open Source since his university days in the early 2000s. Since 2015 he's been heavily involved in Open Source Hardware (FOSSi). He is now the primary maintainer for the OpenRISC Linux kernel, binutils, gdb and gcc ports.

PULP project update

PULP is a RISC-V based multi-core computing platform targeting the requirements of a growing number of end-node Internet of Things (IoT) applications. PULP hardware and software are open-source with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.

In this talk the ORConf community will be updated on the recent developements in the PULP project including releases, demos, application boards, tools.

Presenter: Davide Rossi

Davide Rossi is an assistant professor at the department of Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.

Lessons learned customising the Rocket RISC-V core

This presentation will cover Morse Micro's adaptation of the Berkeley/SiFive Rocket chip generator to suit their needs developing single-chip 802.11ah solutions. We will discuss the pros and cons of Chisel, Rocket's architecture, and aspects of our work in taking the Rocket project and implementing multiple deeply-embedded-class micro-controllers.

Presenter: Julius Baxter

Julius is an engineer at Morse Micro, previously of Broadcom and Qualcomm where he worked as a digital design engineer developing mixed signal wireless ASICs. He was a contributor to the OpenRISC project around 2008-2013, and is a founding director of the FOSSi Foundation.

SpinalHDL : Software generated hardware

SpinalHDL is a Scala based internal DSL which allow describing and generating synthesizable VHDL/Verilog netlist.

The abstraction level of the hardware description API is close to VHDL/Verilog, but by mixing it with the general purpose programming capabilities of Scala, it offer many unconventional and powerful hardware description capabilities, which are the subject of this talk.

Presenter: Charles Papon

Bored of the hardware description languages weaknesses, I initiated the SpinalHDL project 3 years ago and currently I'm working 60% of my time as independent on the development of SpinalHDL and VexRiscv.

Python as a language for testing and code generation

We use Python heavily both for both code generation (FuseSoC + FuseSoC generators), and for testing (VUnit, slvcodec, axilent, pyvivado). I'll describe our setup and briefly introduce the open-source packages that we've created to help our workflow.

Presenter: Ben Reynwar

I'm been working as a RTL Engineer for the last 4 years at Codelucida in Tucson, AZ. Prior to that I spent time working on web development, software-defined radio, stay-at-home-parenting, molecular dynamics simulations, and polymer physics. The projects I'll mention are all packages I've created outside of work hours to help me at work.

fusesoc_generators - For generating code using fusesoc where the generating functions have access to the generic parameters of the module.

slvcodec - Use python to create input stimulus for testing, and check simulation output. Automate creation of test benches and functions to convert to and from std_logic_vector.

axilent - Write python tests for DUT with Axi4Lite interfaces, and run the test against a simulation or against the FPGA.

OpenRISC hardware bootloader over WiFi

Software initialization for System-On-Chip designsis essential and it must be optimal, fast and flexible furtherbe able to manage future updates in a proper way. This work presents a hardware bootloader for theOpenRISC processor where processor code is sent from a central code repository server and received through an ESP8266 WiFi module. A custom hardware module loads the code directly into system’s memory before booting the processor. This approach allows maximum wireless reconfiguration flexibility for a large number of distributed embedded systems, as needed by the IoT and related technologies.

Presenter: Germán Cano Quiveu

Germán is a PhD student at the University of Seville's Department of Electronic Technology.

Look inside your SoC with Open SoC Debug

Open SoC Debug (OSD) is a complete solution for adding debug and trace to a SoC design. It consists of a solid specification, a software and a hardware implementation and supports tracing of CPU cores (RISC-V and OpenRISC currently), memory access (to load your software into the chip), UART emulation, and much more.

Over the last year much effort has been put into the specification and the implementation. New concepts (such as subnets) have been introduced, the software implementation has been fully rewritten and is now more robust than ever, and the hardware has gained significant test coverage (and bug fixing). In addition, run-control debugging is being worked on as part of Google Summer of Code.

This talk gives a quick overview over the Open SoC Debug architecture, and then dives into what changed over the last year.

Presenter: Philipp Wagner

For as long as he could type, Philipp has been interested in software development. Being a real 'full stack' developer, his interests range from hardware design to web development. Making things easier to understand is a recurrent theme in his work. As developer of the LibreCores web site, he works on making digital hardware projects more discoverable. And by adding debug and trace support to SoCs, software development becomes easier on these devices.

Find better cores with LibreCores

LibreCores helps hardware developers find the pieces of code to build their project on. Within the last year finding a suitable "IP Cores" (or LibreCores, as we like to call them) has gotten even easier and faster. With the introduction of the new search and categorization features to LibreCores developers can easily browse through similar cores, filter them and ultimately get their project done faster.

Presenter: Philipp Wagner

Lessons learned while formally verifying the ZipCPU

The ZipCPU is a three-year old CPU and ISA designed for low logic FPGA's. One of the challenges of any CPU design, to include the ZipCPU, is coming up with a sufficiently robust test suite to exercise all of the possible logic flows within the CPU. While formal methods can be used for this task, they are traditionally viewed as too computationally expensive to formally verify something as complex as a CPU.

Contrary to this view, the ZipCPU has now been formally verified using SymbiYosys. As a result, many bugs have been found and fixed--bugs not found previously using canned test cases. Not only that, it has also become easier to modify the CPU as necessary to achieve lower logic utilization, knowing that the formal solver will find any bugs in the updated implementations.

Presenter: Dan Gisselquist

Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His current work is focused on the ZipCPU, the environment, tool-suite, and peripherals necessary to support both it and any customer applications. He is also known for the ZipCPU blog, and has recently taken up training others in formal methods.

Retargeting a legacy ISA CPU core to the RISC-V architecture

The presentation will briefly describe the process of retargeting the proprietary 6-stage legacy ISA CPU core to RISC-V architecture. Two BSc students were assigned for their three-month apprenticeship at ChipCraft and successfully evaluated feasibility and implemented most of User-Level ISA and partly Privileged Architecture specification. Their work will be further continued to achieve full RISC-V compliance. Our future plans are to develop a low-power single stage RISC-V twin core and release it to the open-source community under a GPL license.

Presenter: Krzysztof Marcinek

Krzysztof is an Assistant Professor at Warsaw University of Technology and co-founder of WUT spin-off ChipCraft Sp z o.o.

ChipCraft is a Poland-based fabless semiconductor private company focused on providing custom world class System-on-Chip solutions for precise positioning and Telehealth/Telemedicine wearables markets. The company operations involve also design services in the field of analog, digital, mixed-signal, RF and both analog and digital backend services.

At ChipCraft and WUT Krzysztof is leading a digital research and design team focused on processor architectures, microarchitectures and instruction set extensions.

Clash: Haskell as an HDL

Clash is an effort to build a compiler translating Haskell to Verilog and VHDL. It supports many of Haskell's incredibly powerful constructs, allowing it to reuse much of the existing ecosystem. Clash supports powerful type inference, an interactive REPL, simulation on any target supported by GHC, abstract data types, and higher-order functions. Many hardware features are supported or under active development, such as verilog co-simulation, multiple clock domains, and bidirectional ports.

This talk provides provides a quick introduction into hardware design with Clash.

Presenter: Martijn Bastiaan

During his bachelor's at the University of Twente, Martijn came to know the creators of Clash through his involvement as a TA in the first year's functional programming course. Shortly after starting his studies abroad at Danmarks Tekniske Universitet, the creators founded QBayLogic; a company developing Clash and providing support for it in various forms. Right after graduating he joined the company and has been working there for a year. Since then, he's been an active contributor to the Clash compiler.

Project Trellis: enabling open source tools for the Lattice ECP5 FPGA

Project Trellis documents the bitstream and low-level architecture of Lattice ECP5 FPGAs, which combined with the SymbiFlow tools enables a full open source flow from Verilog source to a bitstream. These FPGAs contain up to 85k logic cells and a range of features including DSPs, multi-gigabit transceivers and advanced IO functionality; unlocking applications such as networking, software-defined radio, high-resolution video, and testing processors powerful enough to run Linux!

The documentation includes core features including logic, RAM and IO tiles. Work continues on both more advanced features and developing a feature-complete open toolchain for the ECP5.

This presentation will discuss what approach was taken and what tools had been developed to create useful bitstream documentation within the constraints of publicly available interfaces; a reflection on what I think worked well and what could have been improved, and how to start you on your way to documenting more FPGA architectures for open source tools - it’s not as scary as you might think!

There will also be a live hardware demonstration of the SymbiFlow open source end-to-end flow for the ECP5.

Presenter: David Shah

David is an engineer at Symbiotic EDA, an open source EDA startup, and a MEng student at Imperial College London; he is passionate about open toolchains for FPGAs. His work on Project Trellis began after seeing the combination of the exciting new ECP5 boards being developed, and the need for larger FPGAs with open tools to enable a wider range of projects and break down misconceptions about the limits of open source.

Previously I have worked on projects including documenting the bitstream of the iCE40 UltraPlus FPGA and adding support to it to the icestorm toolchain.

RISC-V & Renode: towards software-driven development

The open source Renode simulation framework was created in order to enable a software-driven approach to embedded systems development by making it easy to build simulated but binary-compatible SoCs, boards and networks by assembling reusable and object-oriented models. The rapid growth of RISC-V has given a new boost to the framework, as open, configurable CPUs have been transforming the way ASICs and FPGAs are being perceived, designed and worked with. HW/SW co-development and simulation-driven workflows are more natural in an open ISA ecosystem, and with the associated rise of open IPs and tooling, the not-so-distant future looks very promising.

Presenter: Michael Gielda

Michael is VP Business Development at Antmicro with a background in software and AI. He is chairing the Marketing Content TG of the RISC-V Foundation, of which Antmicro is a Platinum Founding Member. Michael was involved with Renode from the very beginning, working with acquiring users/customers, user experience and documentation, defining use cases and workflows.

Another Introduction to Cocotb

An introduction and tutorial on using cocotb and Python to verify your Verilog and VHDL designs. This presentation will cover why you should be using cocotb instead of SystemVerilog and UVM, and its growing usage inside Broadcom, plus an accompanying tutorial on github.

Presenter: Luke Darnell

Luke is an ASIC Design Engineer with 14 years experience working in Broadcom's WCC Business designing WLAN and Bluetooth combo chips. He's based in the WLAN ASIC team and has worked on a wide variety of projects including baseband phy implementations, SOC IP integration, ARM-based CPU subsystem design, AXI/AHB/APB backplane designs, block and chip level design verification, radio modeling, silicon implementation, version control and continuous integration.

He became interested in cocotb after a less than compelling experience with UVM and Verilog/SystemVerilog in general. He got Broadcom to sponsor a number of new features and bug fixes. He continues to use cocotb on a daily basis and evangelizes its use inside Broadcom.

RISC-V ecosystem update

The momentum in the RISC-V ecosystem is incredible, with new implementations, ASIC and FPGA improvements and tools cropping up at an impressive pace. With the first RISC-V Summit just around the corner, it's good to get an update on what's been happening and what to expect next.

Presenter: Michael Gielda

Venue

ORConf 2018 is being hosted by the Gdansk University of Technology.

Gdańsk University of Technology, founded in 1904, is among 9 Polish universities listed by the Times Higher Education World University Rankings. The university consists of 9 faculties with nearly 23,000 students of all cycles, over 1,200 lecturers and it has more than 111,000 graduates. The Faculty of Electronics, Telecommunications and Informatics (ETI) educates about 3,500 students in five fields of studies: Informatics, Electronics and Telecommunications, Control Engineering and Robotics, Data Engineering, and Biomedical Engineering.

ETI is the largest university in Northern Poland in the area of modern technologies, employing nearly 200 researchers and lecturers. The faculty has an extensive research and didactic infrastructure at its disposal. There is also academic computer centre with one of the fastest supercomputer in Europe, as well as a state-of-the art library, anechoic chambers for acoustic research and antenna measurements, modern laboratory of industrial robots, immersive 3d visualization lab, as well as Microsoft and Cadence certified laboratories.

Saturday evening dinner

As is tradition at ORConf, a dinner will be arranged for the Saturday evening (22nd) which all conference attendees and partners are encouraged to attend.

Getting around

We'll provide a guide on getting to and from the conference venue when we can.

Getting there

Air

Gdansk has an international airport and is served by by both major and low-cost airlines, but usefully is a hub for both Ryanair and Wizzair, making it a very affordable city to fly to from most of Europe.

There is a rail line from the aiport into the city which should make transferring from the aiport to accommodation pretty easy. There are further details on this on the Wikitravel page for Gdansk, from which most of this information is cribbed.

Gdansk is also very accessible by rail from all of Europe

Accommodation

Below are some accommodation options for the conference.

Focus Hotel

The Focus Hotel close to the Gdansk University of Technology (a 25 minute walk to the conference) has an offer of a special rate for ORConf visitors this year.

To obtain the offer, go to http://www.focushotels.pl/wydarzenia,165.html, and click on the "Rezerwuj" button next to the ORConf logo.

Once you see the date selection popup, click on "Switch to English" at the top which will make things easier for non-Polish speakers.

Next, and crucially, you'll see a link reading "Enter Code" at the top of the window which should now say "Plan your stay". Click on "Enter Code" and enter ORCONF2018.

You will then see the dates are limited to the dates surrounding ORConf.

Hotels.com

There are numerous options on Hotels.com including Hotel Impresja which appears to be about as far from the conference venue as Focus.

There is a train station for the University (Gdansk Politechnika) which should mean that anyone staying closer to town within reach of a train station should be able to access the venue relatively easily without a taxi.

Trains from Gdansk Central Station (Gdansk Glowny) run about every 10 minutes, taking 5 minutes, until about 10PM at night. So hotels near there would likely be fine as well.

Sponsors

Major Sponsors

Google

Sponsors

AB Open

antmicro

RISC-V Foundation

Gdansk University of Technology - Faculty of Electronics, Telecommunications and Informatics

The event is arranged by the conference committee of the FOSSi Foundation, and they are always looking for sponsors help to cover the costs.
Please get in touch if you'd like to be an ORConf sponsor this year.

You can also support us with small donations via Paypal:


Questions? Contact the organisers or ask in #fossi on irc.freenode.net

We expect all participants of ORCONF to follow the FOSSi Foundation code of conduct.