We're pleased to announce that ORConf 2017 will be held between September 8th and September 10th in Hebden Bridge in the UK.
We are extra-pleased to announce that ORConf 2017 is part of this year's Wuthering Bytes Festival of Technology, which will hold events in Hebden Bridge starting September 1st.
Register to attend this year's event by filling out this form: https://goo.gl/forms/ALKx6xPRZWhaW1sh1
We're now accepting submissions to join us and either present a talk, a poster or host a table with a hardware exhibit. Please submit your proposal via the form here: https://goo.gl/forms/fwALSQvbyUfE83Fh1.
We ask that submissions are made no later than about a month prior to the event, and the sooner the better to help us get an idea of how to schedule things. You can optionally submit a proposal and complete it later (you will be emailed a confirmation with a link to go back and edit your submission), so to help us plan can we ask that if you're confident you'll be attending and presenting, but don't yet have the full contents of the proposal, to at least submit the title, a sentence summary, the type of submission (talk, poster, etc.) and the days you'll be attending.
ORConf is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.
The conference is free to attend, and we invite anyone with an interest in the field to participate by presenting or just joining us for the event. That means we're also looking for sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!
The conference will run from about 12:30PM on Friday until around 3PM on the Sunday, permitting people to travel on the first and last day of the event and not miss any sessions.
The full conference schedule will be made available closer to the time.
Here are summaries of some presentations we'll have at this year's ORConf.
In this presentation, the scaling capabilities of "Many-Core" frameworks are discussed through the demonstration of a parallelized software renderer and massively multi-player online game server.
After the crowd campaign ends, once the design is done, as soon as units start rolling off the factory line, you need to make sure each item is correctly built. We present open-source test jig software built to handle the unexpected problems that are encountered in the factory. Come hear talks about the software, plans for the future, and some horror stories that we've encountered in the factory when developing it.
Presenter: Sean Cross of Kosagi
An update on the progress of the OpTiMSoC multicore SoC project.
The free and open Programming, Design and Verification Language (PDVL) is presented. It comes with an open source EDA framework for PDVL-to-Verilog conversion and PDVL simulation.
Presenter: Tobias Strauch of EDAptix
System Hyper Pipelining (SHP) is a design transformation process. It converts for instance single CPUs into multithreaded CPU. Individual threads can be stalled, bypassed and reordered and can therefore be executed at different speeds. SHP is ideal for FPGAs. An open source project based on an RV32IMAC, the ARTY board and the Arduino IDE is presented during the conference.
Presenter: Tobias Strauch of EDAptix
Kunal will talk about a novel technique of building open-source hardware community using adaptive and adaptable learning mode with open-source EDA tools. The gap confronted here is shortfall of guidelines and support systems to use these tools, and one architecture that connects complete design to all tools. VSD has been attempting to fill this gap by blending the learning and practicing methods through online video courses with the goal of building a large community across the globe who are designing and innovating using open-source tools.
Presenter: Kunal Promode Ghosh of VSD
An automated C-to-GDS flow using open-source EDA tools for medium-sized SOC design and implementation
A poster presentation on a complete C to GDS flow using open source tools demonstrated on a multi-million gate design.
Presenter: Kunal Promode Ghosh of VSD
PULP is a RISC-V based multi-core computing platform targeting the requirements of a growing number of end-node Internet of Things (IoT) applications. PULP hardware and software are open-source with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.
The goal of this talk is to update the ORConf community about the recent developements on PULP including new chips, demos, application boards, software tools and the announced open source release of the PULPinoV2 system.
Presenter: Davide Rossi
Davide Rossi is an assistant professor at the department of Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.
One year ago at ORConf 2016 we announced the work on LibreCores CI - a continuous integration service for projects being hosted on LibreCores. During the last year we made some progress on this front, and we would like to talk about the current project status.
We will show show the project has evolved and present several examples and success stories. Then we will have an open discussion about the system requirements and beta testing.
Stefan is a curious developer and has been involved in the OpenRISC project for many years and is contributor to several other open source projects around SoC design. He is a director at the FOSSi Foundation, where he works on many projects including Continuous Integration prototyping for OpTiMSoC in LibreCores CI.
Oleg is an engineer with R&D and automation background in the embedded processor design area. He is a core team member in the Jenkins open-source project and a newbie contributor to hardware/EDA projects. Oleg is also a major contributor to the FOSSi Foundation's LibreCores project, and the Jenkins-based LibreCores CI work in particular.
The FOSSi Foundation's Licensing committee will present its work on copyleft licensing for HDL and other semiconductor design sources. The focus of the committee's work so far this year has been on determing how to achieve a credible and practical copyleft licensing approach, and in this presentation they will present and discuss their proposed copyleft licence(s).
While some claim to write bug-free software (once it compiles), most of us (voluntarily or not) rely on debugging tools during software development. On a regular desktop PC, the job is usually done by firing up a GDB instance. However, things get a bit more complicated when software runs on an embedded system. A number of challenges arises: remote debugging must be supported, non-intrusive debugging techniques are needed, and all of that with minimal cost to the final chip.
The Open SoC Debug (OSD) project aims to provide infrastructure to enable SoCs to be debuggable. First of all, OSD is a specification of a debug and trace system. The specification describes an architecture and infrastructure components which are essential in a debug and trace system. In addition, OSD comes with a reference implementation of both hardware components to be added to a SoC, and a software implementation which runs on a host PC and connects the user to the chip when debugging.
In this talk, I'll give an overview of Open SoC Debug, revisit what happened in the project since the last ORConf, and given an outlook on what's up next.
For as long as he can type, Philipp has been interested in software development. Being a real 'full stack' developer, his interests range from hardware design to web development. Making things easier to understand is a recurrent theme in his work. As developer of the LibreCores web site, he works on making digital hardware projects more discoverable. And by adding debug and trace support to SoCs, software development becomes easier on these devices.
Philipp is active in the FOSS community and currently serves director of the FOSSi Foundation. He lives and works close to the alps in Munich, Germany.
LibreCores.org is the place to go to when looking for digital hardware projects. In this talk I'll give an overview of the current status, what happened since the the launch at last year's ORConf, and what the future plans are.
Pile of Cores (PoC) is an open source IP core library containing more than 120 IP cores mostly written in VHDL. All IP cores are written in a vendor independent style. If this is not possible or a synthesis tool is not capable of producing the 'best' synthesis result, we implemented a vendor abstraction layer.
Our cores are FPGA-proven and some are even tested in ASIC tool chains. All IP cores offered as source code files with full disclosure. This allows even the usage in security critical or closed source projects. Additionally, the IP cores are shipped with testbenches and synthesis constrains, when needed. If necessary, example projects are provided, too. PoC provides a simple command line interface to simulate, synthesize or package an IP core.
PoC is heavily using free web services to ensure and disclose the quality of PoC's IP cores. That means we are using continuous integration (CI) techniques based on GitHub, Travis-CI, AppVeyor, and GHDL to verify our IP cores. More over, we are using ReadTheDocs to implement continuous documentation!
Mr. Lehmann is one of developers and maintainers of The PoC-Library, a platform and vendor independent open source IP core library. He is also a contributor to the free VHDL simulator GHDL. In 2016, he started an initiative called 'Open Source VHDL Group'.
Mr. Lehmann is active in the IEEE P1076 'VHDL Analysis and Standardization Group' since 2014. He detailed and wrote major parts of the language changes for the upcoming VHDL revision. In 2017 he became an IEEE Standards Association member and was announced vice-chair of the P1076 working group. In June 2017 he started working at PLC2 GmbH as a developer and trainer.
The conference will take place in Hebden Bridge, in the UK.
Hebden Bridge is small enough to be able to walk anywhere within the town.
From Hebden Bridge railway station, follow these Google maps directions to get to the conference venue, Hebden Bridge Town Hall.
Train from Manchester Airport can be as fast as 1h15m to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
Train from Leeds Bradford Airport can be as fast as 1h30m to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
From London and the South, the train is likely to be the best option to get to Hebden Bridge. Journey times can be as fast as 3 hours from London Euston to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
The commute between Halifax and Hebden Bridge is convenient enough to make it a practical alternative to staying in Hebden Bridge.
For example, trains depart on a Friday morning about every 20 minutes and the journey takes 10-15 minutes to get to Hebden Bridge. The return services run at least once an hour in the evening, until the final service just after 11PM. Things look similar on a Saturday and Sunday (last service on a Sunday back to Halifax is slightly before 11PM).
There appears to be several taxi firms operating in and around Halifax, and fares have been quoted at around £15-20 one-way.
There are a few accommodation options available in Hebden Bridge and the nearby minster town of Halifax, West Yorkshire, which is approximately 15 minutes from Hebden Bridge by rail.
Hotels.com list a few properties in Hebden Bridge and around, such as:
- Moyles Signature B&B
- The Hare and Hounds Country Inn
- The Crown Inn
- The White Lion Hotel
- Thorncliffe B&B
- Angeldale Guest House
Airbnb list a number of properties available in Hebden Bridge during the event (as of early May).
The Hebden Bridge Hostel may have availability however it's likely to have already sold out.
Hotels.com list a few properties in Halifax and around, such as:
- The White Swan
- The Imperial Crown Hotel (close to the train station)
- Wool Merchant Hotel
- The Old Post Office
- Premier Inn (short walk to the station)
- Travelodge (a mile walk to the station)
Airbnb list a number of properties also available in and around Halifax during the event (as of early May).
The event is arranged by the conference committee of the FOSSi Foundation, and they are always looking for sponsors help to cover the costs.
Please get in touch if you'd like to be an ORConf sponsor this year.