ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space.
We invite anyone with an interest in the field to join us and also consider a presentation, big or small, on your experience as a developer or a user of open source digital design projects.
ORConf remains to be free to attend thanks to each year's sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!
ORConf is free to attend but you must register.
We encourage anybody involved in the open source semiconductor engineering space to come along and give share your work or experience. Presentations slots as short as 3 minute lightning-talks up to 30 minute talks with Q and A are available.
So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.
The conference will run from about 12:30PM on Friday the 21st until around 3PM on the Sunday, permitting people to travel on the first and last day of the event and not miss any sessions.
The running order will be determined closer to the event.
Below are some of the presentation submissions we've accepted so far.
The primary author of Verilator, the open source high-speed Verilog simulator, announces fresh for this meeting Verilator 4.0 with multithreading, and how you can get your designs' the fast(est), free simulation.
SymbiFlow aims to be the "gcc of FPGAs", a fully open source project which supports multiple FPGAs from many different manufactures. It is currently targeting the Lattice iCE40, Lattice ECP5 and Xilinx 7 series FPGAs.
This presentation will give you an update on the current status of the project. What currently works, the future roadmap and how you can help with the project.
Tim is the founder of TimVideos and is currently heavily involved with the development of the SymbiFlow project.
This presentation will cover Morse Micro's adaptation of the Berkeley/SiFive Rocket chip generator to suit their needs developing single-chip 802.11ah solutions. We will discuss the pros and cons of Chisel, Rocket's architecture, and aspects our work in taking the Rocket project and implementing multiple deeply-embedded-class micro-controllers.
Julius is an engineer at Morse Micro, previously of Broadcom and Qualcomm where he worked as a digital design engineer developing mixed signal wireless ASICs. He was a contributor to the OpenRISC project around 2008-2013, and is a founding director of the FOSSi Foundation.
SpinalHDL is a Scala based internal DSL which allow describing and generating synthesizable VHDL/Verilog netlist.
The abstraction level of the hardware description API is close to VHDL/Verilog, but by mixing it with the general purpose programming capabilities of Scala, it offer many unconventional and powerful hardware description capabilities, which are the subject of this talk.
Bored of the hardware description languages weaknesses, I initiated the SpinalHDL project 3 years ago and currently I'm working 60% of my time as independent on the development of SpinalHDL and VexRiscv.
We use Python heavily both for both code generation (FuseSoC + FuseSoC generators), and for testing (VUnit, slvcodec, axilent, pyvivado). I'll describe our setup and briefly introduce the open-source packages that we've created to help our workflow.
I'm been working as a RTL Engineer for the last 4 years at Codelucida in Tucson, AZ. Prior to that I spent time working on web development, software-defined radio, stay-at-home-parenting, molecular dynamics simulations, and polymer physics. The projects I'll mention are all packages I've created outside of work hours to help me at work.
fusesoc_generators - For generating code using fusesoc where the generating functions have access to the generic parameters of the module.
slvcodec - Use python to create input stimulus for testing, and check simulation output. Automate creation of test benches and functions to convert to and from std_logic_vector.
axilent - Write python tests for DUT with Axi4Lite interfaces, and run the test against a simulation or against the FPGA.
Software initialization for System-On-Chip designs is essential and it must be optimal, fast and flexible further be able to manage future updates in a proper way. This work presents a hardware bootloader for the OpenRISC processor where processor code is sent from a central code repository server and received through an ESP8266 WiFi module. A custom hardware module loads the code directly into system’s memory before booting the processor. This approach allows maximum wireless reconfiguration flexibility for a large number of distributed embedded systems, as needed by the IoT and related technologies.
Germán is a PhD student at the University of Seville's Department of Electronic Technology.
Open SoC Debug (OSD) is a complete solution for adding debug and trace to a SoC design. It consists of a solid specification, a software and a hardware implementation and supports tracing of CPU cores (RISC-V and OpenRISC currently), memory access (to load your software into the chip), UART emulation, and much more.
Over the last year much effort has been put into the specification and the implementation. New concepts (such as subnets) have been introduced, the software implementation has been fully rewritten and is now more robust than ever, and the hardware has gained significant test coverage (and bug fixing). In addition, run-control debugging is being worked on as part of Google Summer of Code.
This talk gives a quick overview over the Open SoC Debug architecture, and then dives into what changed over the last year.
For as long as he could type, Philipp has been interested in software development. Being a real 'full stack' developer, his interests range from hardware design to web development. Making things easier to understand is a recurrent theme in his work. As developer of the LibreCores web site, he works on making digital hardware projects more discoverable. And by adding debug and trace support to SoCs, software development becomes easier on these devices.
LibreCores helps hardware developers find the pieces of code to build their project on. Within the last year finding a suitable "IP Cores" (or LibreCores, as we like to call them) has gotten even easier and faster. With the introduction of the new search and categorization features to LibreCores developers can easily browse through similar cores, filter them and ultimately get their project done faster.
Presenter: Philipp Wagner
The ZipCPU is a three-year old CPU and ISA designed for low logic FPGA's. One of the challenges of any CPU design, to include the ZipCPU, is coming up with a sufficiently robust test suite to exercise all of the possible logic flows within the CPU. While formal methods can be used for this task, they are traditionally viewed as too computationally expensive to formally verify something as complex as a CPU.
Contrary to this view, the ZipCPU has now been formally verified using SymbiYosys. As a result, many bugs have been found and fixed--bugs not found previously using canned test cases. Not only that, it has also become easier to modify the CPU as necessary to achieve lower logic performance, knowing that the formal solver will find any bugs in updated implementations.
Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His current work is focused on the ZipCPU, the environment, tool-suite, and peripherals necessary to support both it and any customer applications. He is also known for the ZipCPU blog, and has recently taken up training others in formal methods.
ORConf 2018 is being hosted by the Gdansk University of Technology.
Gdańsk University of Technology, founded in 1904, is among 9 Polish universities listed by the Times Higher Education World University Rankings. The university consists of 9 faculties with nearly 23,000 students of all cycles, over 1,200 lecturers and it has more than 111,000 graduates. The Faculty of Electronics, Telecommunications and Informatics (ETI) educates about 3,500 students in five fields of studies: Informatics, Electronics and Telecommunications, Control Engineering and Robotics, Data Engineering, and Biomedical Engineering. ETI is the largest university in Northern Poland in the area of modern technologies, employing nearly 200 researchers and lecturers. The faculty has an extensive research and didactic infrastructure at its disposal. There is also academic computer centre with one of the fastest supercomputer in Europe, as well as a state-of-the art library, anechoic chambers for acoustic research and antenna measurements, modern laboratory of industrial robots, immersive 3d visualization lab, as well as Microsoft and Cadence certified laboratories.
As is tradition at ORConf, a dinner will be arranged for the Saturday evening (22nd) which all conference attendees and partners are encouraged to attend.
We'll provide a guide on getting to and from the conference venue when we can.
Gdansk has an international airport and is served by by both major and low-cost airlines, but usefully is a hub for both Ryanair and Wizzair, making it a very affordable city to fly to from most of Europe.
There is a rail line from the aiport into the city which should make transferring from the aiport to accommodation pretty easy. There are further details on this on the Wikitravel page for Gdansk, from which most of this information is cribbed.
Gdansk is also very accessible by rail from all of Europe
Below are some accommodation options for the conference.
The Focus Hotel close to the Gdansk University of Technology (a 25 minute walk to the conference) has an offer of a special rate for ORConf visitors this year.
To obtain the offer, go to http://www.focushotels.pl/wydarzenia,165.html, and click on the "Rezerwuj" button next to the ORConf logo.
Once you see the date selection popup, click on "Switch to English" at the top which will make things easier for non-Polish speakers.
Next, and crucially, you'll see a link reading "Enter Code" at the top of the window which should now say "Plan your stay". Click on "Enter Code" and enter ORCONF2018.
You will then see the dates are limited to the dates surrounding ORConf.
There is a train station for the University (Gdansk Politechnika) which should mean that anyone staying closer to town within reach of a train station should be able to access the venue relatively easily without a taxi.
Trains from Gdansk Central Station (Gdansk Glowny) run about every 10 minutes, taking 5 minutes, until about 10PM at night. So hotels near there would likely be fine as well.
The event is arranged by the conference committee of the FOSSi Foundation, and they are always looking for sponsors help to cover the costs.
Please get in touch if you'd like to be an ORConf sponsor this year.
We expect all participants of ORCONF to follow the FOSSi Foundation code of conduct.