ORConf

We encourage anyone involved in the open source semiconductor engineering space to come along and give share your work or experience.

This year we're offering lightning talk and 15-minute speaking slots, with the choice of opting in to be considered for an extended slot of 30-40 minutes. We are intentionally reducing the standard speaking slot length this year to ensure we can accomodate all of the exceptional talk submissions we recieve, and to maximise face-to-face time throughout the event. We encourage speakers to skip the technical deep-dive presentations and instead provide high-level introductions and overviews of what makes their work great, and prepare a poster or hardware demo for people to come and discuss details during the breaks.

So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.

Skywater130 PDK is very popular among academia and microelectronic hobbyists, as it is open source and no NDAs need to be signed in order to get access to it. It can be used for manufacturing chips, as several tapeouts have proved. Cadence has developed a version of the PDK, which supports such Cadence tools like Virtuoso Studio, PVS, Spectre and Xcelium. In the workshop the attendees will be able to collect first experience with the PDK and Cadence tools, try to design a standard cell, simulate and verify it. The hand-ons are based on the VLSI Fundamentals Education Kit, which is in process of being ported to Skywater130 PDK.

The workshop will find place at Cadence Design Systems office in Feldkirchen in vicinity of Munich. Address: Mozartstrasse 2, 85622 Feldkirchen. It can reached by S2 from the center of Munich. The workshop will start at 14:00 - 18:00. After that Cadence is inviting for a get-together at Locanda Bisignano, Clara-Schumann-Strasse 2 in Feldkirchen.

Cadence tools will be provided through Europractice cloud. Please bring your own laptop, you will connect via RDP to the cloud, where you will be able to start the tools.

In order to register to the workshop, please write an email to aklotz@cadence.com

ORConf Sunday Sessions on Sept 17 are an opportunity for projects and developers to get together and have in-depth discussions in a format they prefer.

cocotb unconference

The cocotb unconference is an interactive venue for all cocotb users and developers. There is no fixed format or schedule for this event: everyone is invited to bring their own topics to discuss, or just to listen in to other discussions.

About cocotb: cocotb is the most widely used Python-based hardware verification framework. cocotb lets you verify chips like software: productive, simulator-agnostic, in Python.

Read more about this event in the cocotb blog.

Organizer: Philipp Wagner and the cocotb maintainers

FuseSoC Plugfest

Got a core written by yourself or someone else and want to add FuseSoC support for it? Would you like to get help porting a FuseSoC-packaged design to your favorite FPGA board or run it in your favorite simulator? Want to discuss adding new features or support for more tools and flows to FuseSoC and Edalize? Got other ideas? Either way, we're here for you to help out, inspire and collaborate to make the FuseSoC ecosystem even better. We will also run a high score table and see for how many IP cores we can add FuseSoC support during the event. Drop in anytime during the event to participate. Welcome!

The award-winning FuseSoC is the most widely used package manager for HDL designs and allows users to easily share, use and reuse cores as well as providing a tool agnostic iinterface that lets you use your designs with almost any EDA tools such as simulators, FPGA toolchains, linters and formal verification tools.

Organizer: Olof Kindgren and the FuseSoC/Edalize team

Tiny Tapeout - design your own chip and get it made!

In this workshop you will get the opportunity to design and have manufactured your own design on an ASIC!

You will learn:

• The basics of digital logic,
• The basics of how semiconductors are designed and made,
• How to use an online digital design tool to build and simulate a simple design,
• How to create the GDS files for manufacture on the open source Sky130 PDK.

Participants will have the option to submit their designs to be manufactured on the next shuttle as part of the Tiny Tapeout project.

Participants will need a laptop. Mouse and headphones strongly advised. Nothing needs to be downloaded, but good internet is required.

Organizer: Matthew Venn

OpenROAD: The journey so far and roadmap

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OpenROAD is an open-source RTL-to-GDS tool that generates manufacturable layout from a given hardware description – in 24 hours, at advanced foundry nodes. OpenROAD lowers the cost, expertise and schedule barriers to hardware design, thus providing a platform for research, education and system innovation. This talk will first review highlights and lessons learned from OpenROAD’s 5-year journey since June 2018. The talk will then present current status and challenges, as well as a roadmap for OpenROAD as it seeks to enable VLSI/EDA education, early design space exploration for system designers, research on machine learning in EDA, and more.

Presenter: Andrew Kahng (UC San Diego)

Andrew B. Kahng is Distinguished Professor of CSE and ECE and holder of the endowed chair in high-performance computing at UC San Diego. He was visiting scientist at Cadence (1995-97) and founder/CTO at Blaze DFM (2004-06). He is coauthor of 3 books and over 500 journal and conference papers, holds 35 issued U.S. patents, and is a fellow of ACM and IEEE. He was the 2019 Ho-Am Prize laureate in Engineering. He has served as general chair of DAC, ISPD and other conferences, and from 2000-2016 served as international chair/co-chair of the International Technology Roadmap for Semiconductors (ITRS) Design and System Drivers working groups. He has been principal investigator of “OpenROAD” (https://theopenroadproject.org/) since June 2018, and until August 2023 served as principal investigator and director of “TILOS” (https://tilos.ai/), a U.S. NSF AI Research Institute.

Caliptra: Building Open Source Security IP with Open Source Tools

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Building a modern, complex, RISC-V based digital design like the Caliptra Root of Trust requires collaborative effort between multiple development teams of various backgrounds, especially in standards-based multi-organization environments like CHIPS Alliance. While in software development massive, standards-driven collaboration is a reality through open source infrastructure and tools, this success needs to be replicated in the hardware space with open source tooling to easily share and automate workflows, scale continuous integration and enable security through transparency of the development process. In this talk we will describe how digital design tools and workflows developed and used by CHIPS Alliance - including Verible, OpenROAD, cocotb, Verilator are being used in practice in a collaborative environment as a potential template for other work in this space.

Presenter: Michael Gielda (Antmicro)

Ten Years of PULP: The Evolution of the Species from IoT to HPC

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With the increasing number of applications across various sectors such as IoT, consumer electronics, industrial automation, automotive, and high-performance computing silicon IPs leverage silicon IPs as fundamental building block for creating complex electronic systems. While the cost of accessing silicon has been decreasing due to the twilight of Moore’s law, obtaining proprietary hardware IPs remains a significant obstacle for innovative start-ups and can also lead to apply chain challenges for larger companies. However, a recent surge in high-quality open-source hardware IPs offers a promising solution to overcome this barrier. These advancements pave the way for exciting applications in open-source electronics, potentially alleviating supply chain issues for global electronics system design companies. In this presentation, I will delve into the evolutionary journey of the open-source Parallel-Ultra-Low-Power (PULP) platform over the past decade exploring opportunities and challenges for next-generation open-source computing systems in a wide range of domains, from IoT to HPC.

Presenter: Davide Rossi (University Bologna)

Opening

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Presenter: FOSSi Foundation team

Module with CologneChip GateMate FPGA (GMM-7550)

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Presentation (with a live demo) of the open hardware module, based on the CologneChip GateMate FPGA. Hardware part of the project consists of the FPGA module itself, a small adapter board to host the module on Raspberry-Pi 40-pin GPIO header, a memory (SRAM and SPI) extension module, control software, and design examples. GateMate FPGA designs are synthesized using the Yosys framework, optionally with GHDL Yosys plugin. All the hardware was designed with KiCAD and released under CERN-OHL-P license. Control software and design examples are released under MIT license.

Presenter: Anton Kuzmin

Anton Kuzmin has thirty years of embedded systems design experience covering hardware, embedded and real-time software, and FPGA development as well as managing projects. The GMM-7550 module had started as a self-education exercise with a new FPGA vendor and family and as an easy way to get a convenient platform for experiments.

Old School cache coherence - a snooping system for a multicore processor based on CVA6

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For many years now the computational power required by modern applications can only be offered by a collection of CPUs working together in a multicore processor. For these CPUs to process information correctly, it is necessary to implement mechanisms which guarantee that each core always uses an up-to-date version of the data: cache coherence protocols have been developed with this purpose. Years ago, when silicon technology could support the integration of only a handful of CPUs per chip, cache coherence was achieved by implementing bus snooping mechanisms; nowadays the propensity is to make use of directory-based cache coherence mechanisms, which guarantee excellent scalability, at the expense speed. This trend can be confirmed also by looking at the existing open-source implementations: there is not a single snooping mechanism. This is a problem, because many real-world scenarios would benefit from a low latency cache coherence unit, for example for all processors integrating a limited number of CPUs. With Culsans our goal is to cover this gap, by developing an open-source, tightly-coupled, low latency cache coherence unit for a quad-core processor based on the popular RISC-V CPU CVA6. In this presentation we show the architecture and the performance of the proposed implementation.

Presenter: Massimiliano Giacometti (PlanV GmbH )

Founder and Managing Director of PlanV, Massimiliano is a RISC-V and open-source enthusiast: he has been working as hardware designer for his entire career, having contributed to a wide range of projects and products, from signal processing and communication systems to computer architectures.

Early performance estimation using virtual prototypes and open-source SW

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Virtual Prototypes (VP) enable early software development and verification. In addition, VP models can be extended to provide information for early architectural analysis. Based on SystemC, specifically TLM2 based modeling, VPs can offer simulations of complete hardware platforms with significantly higher speeds and less overhead than RTL simulations. Using productivity libraries has a significant impact on the development effort. But often such productivity libraries are tied into vendor specific tooling. We will show an alternative approach based on open-source libraries. The analysis process can also be significantly eased with the use of open-source analysis packages. We will show how we use open-source Python libraries to analyze results from VP and early architecture simulations.

Presenter: Rocco Jonack (Minres GmbH)

Rocco Jonack received his master’s degree in electrical engineering from RWTH Aachen. Over more than 25 years he worked on various aspects of SoC development and architecture with a focus on using higher abstraction levels for architecture, implementation, and verification.

Virtual Prototypes and Open Source Hardware Design in Research and Education

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Virtual Prototypes (VP) enable early software development and verification. Furthermore, they additionally VPs allow flexible hardware prototyping. Based on the SystemC hardware modeling language, VPs can offer fast simulations of complete hardware platforms (e.g., System-on-Chip (SoC)) executing bare metal applications, operating systems and more (10x to 100x faster than RTL simulations). With the Group of Computer Architecture (AGRA) at the University of Bremen, our research focuses on methods and techniques for the design and verification of VP-based Software and Hardware. To bridge the gap between the VP and the real-world Hardware, methods crossing the abstraction layers (e.g., from the VP to the RTL) is a promising approach for verification. While utilizing available open source tools, we take part in releasing our tooling as open source to enable further research and offer accessible educational tools (VPs, RTL implementation, verification tools, etc.). In this talk, we will give an overview of our recent workaround VPs, design and verification and how open source helps in research and education.

Presenter: Sallar Ahmadi-Pour (Group of Computer Architecture, University of Bremen)

Sallar Ahmadi-Pour received his master’s degree in computer science from the University of Bremen, Bremen, Germany, in 2020, where he is currently pursuing his Ph.D. degree with the Research Group of Computer Architecture. His current research interests include the design and verification of embedded systems across multiple levels of abstraction.

RADOPA: Robustifying a Design Against Optical Probing Attacks

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Recent studies revealed that laser-based side channel attack methods, especially Optical Probing (OP), pose a serious threat to the security of integrated circuits. State-of-the-art countermeasures focus mainly on approaches in the domain of circuit design, and lack appropriate analysis methods that can be employed during design time. Consequently, the actual robustness against OP can only be tested during post-fabrication, which might lead to the necessity of IC redesign. To mitigate this problem, we propose the framework RADOPA that enables already during design time exploring the circuit’s susceptibility against OP. The main elements of this framework are reading layout file, performing logical computation, and performing various OP analysis such as retrieving internal waveform of chips, and creating activity map of area of interest on chip. The applicability of our framework, namely RADOPA is explored by designing and verifying a cell library and exemplary circuits that are robust against OP attacks. We will demonstrate OP on cell libraries based on a 45nm open-source PDK and its standard cell library, and provide a guide on how to robustify a design against OP attacks. Moreover, we evaluate layout design techniques that can alleviate the OP attacks. We will provide all the explored cell libraries in this work and the core engine to perform OP in order to replicate the results publicly available. As a future plan, we are aiming to make our tool source files publicly available.

Presenter: Sajjad Parvin (University of Bremen)

Sajjad Parvin received his B.Sc. degree in electronics engineering from Hormozgan University, Iran, in 2016. Then he joined the ECC group at Istanbul Technical University, Türkiye, where he worked as a TUBITAK researcher and received his M.Sc. degree in electronics engineering in 2020. He is currently pursuing his Ph.D. with the University of Bremen, Germany, in the field of hardware security at the layout level. His current research interests are EDA, AI accelerators, and the design of secure chips.

OpenRISC update 2023

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An update about what is new and and upcoming with the OpenRISC architecture, one of the first open source CPU architectures.

Presenter: Stafford Horne (OpenRISC )

Stafford Horne is a computer engineer, working in finance at a Japanese mega bank SMBC. He works on open source hardware and software as a hobby.

Visualizing and exploring open-source microchips

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This talk is about the landscape of visualizing and exploring the inside of microchips with open-source projects. Three manufacturable Process-Design-Kits (PDK) got published under open-source licenses so far and the count is increasing. These PDKs drive attention and workforce into open-source Electronic-Design-Automation (EDA) projects. Besides the well-known and recognized open-source EDA design flow tools (OpenRAOD and -LANE, Klayout, Magic, a.s.o) some smaller and niche projects enable new, creative and even innovative methods and provide tools for education. An overview and list of available and active tools and projects for visualizations will be given. You are free to use all of them without signing non-disclosure agreements (NDA) or buying high-priced licenses for your teaching, education, research and what else you want to make of it. Did you ever hold a 3D-printed AND-Cell in your hands? Do you want to fly through your rendered GDSII file? Some real-world examples to open up further discussions will be presented.

Presenter: Thorsten Knoll (RheinMain University of Applied Sciences)

Thorsten is a computer scientist and cares about open-source hardware. Currently, he works as a researcher at RheinMain University of Applied Sciences and tries to produce as many open-source microchips as possible. He is on the author list of the open-source IHP130 PDK and has a soft spot for creating physical stuff.

Effective Timekeeping in RISC-V Processors: Overview of mtime Design Approaches

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Timers are an integral part of most processors, serving essential tasks such as preemptive context switching or reading sensor values at specific time intervals. The RISC-V specification defines the mtime counter as part of their High-Performance-Counter facility to provide RISC-V processors with a stable wall-clock time. This counter is unique, however, as it is the only counter that is accessed through memory-mapped registers instead of control and status registers (CSRs). This has implications for the design of the mtime counter, making it challenging to find a design that best fits the project’s requirements. Within this presentation, the mtime counter is explained and multiple design strategies of the mtime counter are shown and compared to each other. Furthermore, a modified mtime counter is proposed that exclusively relies on a CSR-based implementation. Such CSR-based implementations exhibit greater consistency within the High-Performance-Counter facility and are generally more lightweight in terms of area and access time than their memory-mapped counterparts. This makes them particularly well-suited for deeply-embedded cores where known operation conditions can be utilized to achieve smaller core area.

Presenter: Viktor J. Schneider (Infineon Technologies AG, Leibniz Universität Hannover)

Viktor Schneider is a master’s student in Computer Engineering at Leibniz Universität Hannover. His study focuses on ASIC and processor design. In the last months, he pursued an internship at Infineon in Munich, where he worked on implementing a highly configurable RISC-V core generator that targets applications requiring hardened designs.

CHIPS Alliance Open Source Digital Design Tooling Updates

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Linux Foundation’s CHIPS Alliance project propagates the development and use of open source tooling for ASIC and FPGA design to bring a more software-oriented mindset into the hardware world. The Tools Working Group within CHIPS is concerned specifically with digital design tools which cover simulation, synthesis and place and route, IP aggregation, linting, formatting and more.

In this talk, the Chair of the Tools WG will discuss recent developments in the group’s projects such as RISC-V DV, Verible, Surelog/UHDM, SystemVerilog synthesis, custom GitHub runners for mass CI, improvements in Verilator and more.

Presenter: Karol Gugala (Antmicro / CHIPS Alliance)

Karol Gugala is Engineering Manager at Antmicro, where he leads the software team and works with open source in various contexts - digital design, AI and low level software. An open source enthusiast involved in a wide variety of FOSS projects and Chairman of CHIPS Alliance Tools Workgroup.

RISC-V Instruction Set Extensions for Cryptography - From Research to Standardization

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The introduction of RISC-V democratized the discussion about the features of an instruction set architecture. Cryptographers made extensive use of this possibility and made various proposals for the secure and efficient integration of different cryptographic schemes. In 2021, a first volume of RISC-V cryptography extensions was ratified. This talk summarizes various proposals for extensions that were made by researchers, if and how they made their way into RISC-V, and what the future of cryptographic extensions might look like.

Presenter: Felix Oberhansl (Fraunhofer AISEC)

Felix Oberhansl is a research associate for secure hardware design at Fraunhofer AISEC. His research interest include efficient and secure design of lightweight and post-quantum cryptography.

lowRISC overview and update

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lowRISC is a not-for-profit organization headquartered in the UK whose mission is to make open source silicon a widely used commercial reality. We steward OpenTitan, an open silicon root of trust. Our engineers work in collaboration with OpenTitan partners to produce open RTL, DV, documentation and software developed live on our open repository. We recently achieved a tape-out of our first engineering sample with chips expected in November in preparation for volume production.

This talk gives an overview of lowRISC and the OpenTitan project, an update on our latest achievements and a look into our future plans. It includes details on some of our most interesting and significant IP (such as Ibex our RISC-V core) with pointers on how you can use it in your own designs.

Presenter: Greg Chadwick (lowRISC)

Greg is the digital design lead at lowRISC, where he has been working for the past 4 years. Previously he was at Arm, working on memory systems for A-class cores and at Broadcom working on GPUs. At lowRISC he’s worked on many aspects of OpenTitan and Ibex, our RISC-V core.

GoIT: European initiative for free and open silicon

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Europe’s IT hardware development is constantly challenged by outrageously expensive design tools, legal constraints like NDAs or patents, lock-in threats, dependency on external vendors and supply chains, and foreign political events. The hardware development is expensive and inefficient and undermines the very principles of sovereignty, resilience and reusability. Free and open-source silicon chips carry the potential to catapult Europe into a renaissance of digital technology. The “Go IT!” project focuses on maximizing the openness of software and hardware, creating suitable open-source hardware licences, finally enabling RTL and non-RTL component reusability, fostering the availability and compatibility of PDKs and design tools, providing the root of trust primitives, identifying essential standards for open-source silicon, providing feedback to the European policymakers and facilitating general awareness of the challenges, threats and opportunities for free and open-source silicon.

Presenter: Rihards Novickis (EDI)

Rihards Novickis is a senior researcher at the Institute of Electronics and Computer Science, also internationally known as EDI. He leads the System-on-Chip research group and is involved in a wide range of technical activities ranging from RTL accelerator design for various image processing challenges and embedded Linux kernel development to scalable system architectures and technical team management. The main objective of his research is to create novel computing concepts and approaches, thus ensuring a sustainable advancement of our society.

Blackwire: WireGuard in HDL at 100+ Gbit/s

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Blackwire is our HDL/RTL WireGuard protocol targeting FPGA NIC boards and stacks, accelerating the state-of-art VPN protocol inline and at 100 Gbits/s wire speeds. We started from scratch, and now with the most critical parts finished, 75% done, released the project open-source. The presentation will show architecture and a pipeline example.

Presenter: Leon Woestenberg (BrightAI B.V.)

Leon Woestenberg is Sr. Principal Systems Architect at BrightAI with a focus on hardware and software design for heterogenous systems (CPU/SoC/FPGA). Previously worked on enabling FPGA for the cloud (used in Amazon AWS F1, etc.), now working on bringing the state-of-art and piece-of-art WireGuard VPN protocol into the FPGA and ASIC world as lead architect and engineer.

Data transport in a radio telescope: Remote Direct Memory Access over Ethernet from FPGA to GPU

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In the past century, many discoveries have been made in the universe through radio astronomy. Several discoveries of recent years include Pulsars, Fast Radio Bursts and the magnetic interaction between stars and their planets. Contrary to an optical telescope, a radio telescope observes a range of radio signals outside the optical spectrum. Today’s radio telescope systems consist of several to many antennas which are computationally combined into one large radio telescope.

To enable more groundbreaking research, even better systems are needed to reveal more details of the universe. At the same time, there is a pressing need to improve the material cost and energy efficiency of systems. One of the biggest challenges we face today is efficient data movement from antenna receivers to the GPUs in the central processor that performs most of the computational work.

This talk will first give an introduction in to radio telescope systems and will then discuss how an implementation with Remote Direct Memory Access (RDMA) over Converged Ethernet (RoCE) from FPGA to GPU can both improve the energy efficiency of radio telescope systems as well as enabling new science. The RoCE implementation on FPGA is under development and will be made available as open firmware.

Presenter: Steven van der Vlugt (ASTRON)

Steven works as Researcher High Performance Computer Systems at ASTRON. He (pre)develops SW, FW and systems with GPU, FPGA and CPU for applications in radio astronomy.

ASTRON's open source IP contributions

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Introduction to open source tooling and IP for FPGA design developed or used at ASTRON. The goal of this talk is to communicate a high level overview of our design flow and open source tooling. As well as the open source IP we have provided in the past and touch on recent open-source projects we work on.

Presenter: Reinier van der Walle ( ASTRON Netherlands Institute for Radio Astronomy)

Reinier van der Walle works as a digital design engineer (FPGA firmware engineer) who coordinates the Real-time-systems-development (RTSD) team at ASTRON. The RTSD team is responsible for design and implementation of the real-time digital back-end of ASTRON’s radio telescope systems. Some projects Reinier is involved in are the LOFAR2 upgrade and DISTURB to develop the digital data-path at station level (filtering, correlation, beamforming, etc.). More recently, Reinier started on the RADIOBLOCKS project to design and develop an open-source RDMA over converged ethernet (RoCEv2) IP core.

A reusable verification, emulation and validation flow for ASIC design

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In the conventional ASIC design life cycle, distinct teams are assigned to ASIC design/verification, firmware design/verification, and software development, leading to separate timelines and potential communication gaps. Consequently, issues detected during firmware or software phases can be challenging and expensive to correct.

The presented reusable approach allows all teams to work concurrently, ensuring improved coordination and faster development cycles. Moreover, it facilitates the majority of the work to be completed even before the final silicon is ready, resulting in a more robust and efficient ASIC design process.

We present a practical implementation of an reusable design flow that uses open-source tools.

Presenter: Tomasz Hemperek (Dectris AG)

Tomasz is an ASIC designer, physicist and a cocotb maintainer.

Open source design testing and verification with UVM and Verilator

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The presentation will discuss the current status of non-synthesizable SystemVerilog support in the Verilator open source simulator. The talk will shed light on the latest developments on the way towards full Universal Verification Methodology (UVM) support and discuss future plans, including constrained optimization support and process control enhancements. The talk will also cover improvements in the areas of memory footprint reduction and testing speed acceleration for complex digital designs.

Presenter: Krzysztof Bieganski (Antmicro)

Krzysztof is a senior software engineer at Antmicro. In his everyday work, he focuses mostly on open source SystemVerilog tooling. He is one of the main contributors to Verilator, responsible for, besides other things, implementation of the stratified scheduler functionality in Verilator.

How cocotb made Python-powered verification mainstream -- and what comes next

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cocotb is now a synonym for Python-powered hardware verification. In this talk, we’ll celebrate what cocotb has achieved by looking back, but more importantly, by looking forward.

Presenter: Philipp Wagner (cocotb)

Philipp Wagner is a verification engineer at IBM during daytime, and Director at the FOSSi Foundation and cocotb maintainer at night. He’s been involved in open source software and hardware since he can type and still can’t get enough of it. Philipp was awarded a PhD (Dr.-Ing.) in Electrical Engineering from Technical University Munich for work on software observability in embedded systems.

SystemVerilog Testbench linting with open-source

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Abstract— Linting or rule-checking is a proven technique in RTL design and software domain to maintain high quality of code across distributed teams. SystemVerilog, the leading design verification language for chip designs will immensely benefit from such technology/process. However, lack of focus in EDA, wide variety of coding styles, and commercial factors have slowed down development of such tools in the past. We present our experience in building and deploying such lint tools based on a popular open-source platform slang/pyslang. As rules are developed in Python, it is very easy to customize it at finer granularity with reasonable cost. We also share how such rule checking can be integrated into a Continuous Integration/development (CI/CD) flow such as Git Actions.

Presenter: Srinivasan Venkataramanan, Satinder Singh Paul (AsFigo Technologies)

Srinivasan Venkataramanan (Srini) is an influencer and a technology entrepreneur with extensive knowledge of Semiconductor chip design flow, languages, tools, and methodologies. As part of his latest venture, AsFigo Technologies, he is mainly focused on applying the latest technologies to address current bottlenecks in the chip design and verification process, with specific focus on open-source based deployments. Srini is also a keen contributor to the open-source ecosystem and contribute to flows, tools, and libraries.

MathLib - Math functions Library for SystemVerilog

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The importance of mathematical models in modern electronic-based systems across various domains such as automotive, telecommunication, gadgets, and medical cannot be overstated. These models play a central role in system design and are often created using tools like MATLAB© and Octave, which offer a wide range of built-in functions. However, hardware design, particularly the verification process, requires specialized skills and tools like SystemVerilog.

To address this, we have developed a package called MathLib, which extends standard SystemVerilog to include mathematical function modeling. In this paper, we present a selection of MATLAB functions and their equivalents implemented in MathLib. This approach offers several key advantages:

1. Native SystemVerilog implementation: By integrating mathematical functions directly into SystemVerilog, we eliminate the need for external tools or dependencies, streamlining the design process.

2. Cost savings: Since MathLib enables native implementation in SystemVerilog, it eliminates the need for additional licenses or software, resulting in cost savings for the users.

Furthermore, we provide a real-world example of how MathLib was utilized in one of our recent customer projects. We demonstrate how we employed MathLib to model complex equations within native SystemVerilog, showcasing its practical application. Additionally, we share insights from deploying this library in a few analog and mixed-signal (AMS) designs, specifically in the development of designs such as low-dropout regulators (LDOs) and low-pass filters (LPFs).

Through this paper, we aim to highlight the benefits of using MathLib in SystemVerilog-based design projects, showcasing its capabilities and demonstrating its successful integration into various AMS designs.

Presenter: Deepa Palaniappan, Srinivasan Venkataramanan (AsFigo Technologies)

Deepa Palaniappan (deepapln@yahoo.com) is a seasoned engineer working on multiple disciplines in IC design and verification. Her interests include open-source simulators such as Verilator, Icarus and libraries/frameworks such as GO2UVM, SVUnit etc. She contributes to few open-source projects such as SVA IP on Verilator, MathLib development etc. She is consulting on FPGA design and verification to remote clients based in Europe.

spinal.lib.bus.tilelink : An Tilelink interconnect generator based on fiber

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This talk will present a Tilelink interconnect generator recently developped in SpinalHDL. Unlike rocket-diplomacy, it leverage the fiber paradigm (~coroutines) to negociate/propagate parameters and elaborate the hardware, while being fully decentralized. The goal of this aproache being to provide a more aprochable and flexibility tool.

Presenter: Charles Papon (SpinalHDL)

Charles Papon as an open-source developper based in Basel

A Graphical Guide to Lightweight Block-Level Formal Verification

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Shorter design cycles and the need for customized digital designs due to tight constraints on performance, power consumption, area, and security raise the risk of overlooked bugs. Traditional verification techniques based on simulation can only test a limited set of sequences and might fail to stimulate an error. Formal verification, on the other hand, explores the state space and proves a property exhaustively on the given design under the given assumptions. It can find rare corner-case issues within seconds and spot ambiguities in the specification. Arguing over whole classes of stimuli concurrently, however, requires different thinking and comes with a learning curve when used to simulation. We present a flow-chart-based methodology for lightweight block-level formal verification aimed at designers. We focus on open-source tools in the given examples to motivate utilizing formal verification in the following projects.

Presenter: Meinhard Kissich (Graz University of Technology)

Meinhard Kissich is a Ph.D. student at Graz University of Technology (TU Graz) in Austria, studying and researching FPGA backend flows, exploitation of physical effects in FPGAs, and applied formal verification. Prior to joining the Embedded Automotive Systems (EAS) Group, he worked at various electronics and semiconductor companies while pursuing his studies. In 2022 he achieved a Master’s degree with distinction in Information and Computer Engineering from Graz University of Technology, after obtaining a Bachelor’s degree in the same field. Meinhard Kissich’s educational journey is not just about the acquisition of knowledge but also about sharing it. During his studies, he was involved as an assistant in Control Systems and held lecture units. He now leads the Real-Time Operating Systems Laboratory course and supports the related lecture held by his Ph.D. supervisor Prof. Marcel Baunach. Apart, Meinhard Kissich thrives on engaging in unique ideas outside convention and evaluating the found solutions.

Bluespec is my favourite HDL and here's why

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q3k will recount his story of learning and then using Bluespec HDL in his OpenMPW toy project. He will quickly introduce the language, explain why he’s excited for it, and provide a retrospective on his experiences using it.

Presenter: Serge 'q3k' Bazanski (n/a)

q3k is a generalist of many trades, sometimes dabbling in digital logic and open silicon.

He enjoys bringing in software engineering methodology to other domains, from hardware development to datacenter operations.

Python Filter Design and Analysis (pyfda) - an easy to use tool for floating point and fixpoint filters

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Presentation with a live demo of the open source software pyfda with a user-friendly GUI. After a general introduction, some of the features will be highlighted that are useful for FPGA or microcontroller design.

Presenter: Christian Muenker (Munich University for Applied Sciences)

Christian Muenker teaches analog electronics and digital signal processing at the Munich University for Applied Sciences, after having designed mixed-signal and RF SOCs professionally for 14 years. While he initially developed pyfda as a tool for teaching digital signal processing, he has added more export options to increase the usefulness for hard- and software design.

Tiny Tapeout update

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TinyTapeout 4 closed last week - what happened and next steps

Presenter: Matt Venn (tinytapeout, zero to asic course)

SystemRDL: CSR description language everyone wished for

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Presenter: Marek Pikuła

Coriolis 2.5 update!

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Presenter: Rob Taylor

FuseSoC in Three Minutes

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Presenter: Olof Kindgren

Renode - open source systems simulation framework

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Presenter: Michael Gielda

WaveDrom

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Presenter: Aliaksei Chapyzhenka

SERV - A quick talk about a small CPU

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Presenter: Olof Kindgren

Hardware: A messy landscape we all love

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Presenter: Michael Gielda

GateMate Module Crowdsourcing

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Presenter: Anton Kuzmin