September 27th to 29th in Bordeaux, France.
The FOSSi Foundation are pleased to announce ORConf 2019 will be taking place in beautiful Bordeaux, France over the final weekend of September, 27th to 29th, 2019.
We are currently planning the event, so check back for updates over the next month or so.
ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space.
We invite anyone with an interest in the field to join us and also consider a presentation, big or small, on your experience as a developer or a user of open source digital design projects.
ORConf remains to be free to attend thanks to each year's sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!
ORConf is organized by the Free and Open Source Silicon (FOSSi) Foundation.
Questions? Contact the organisers.
ORConf is free to attend! We require that you register so so we know how many to expect.
Attendees who are joining us at ORConf on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at ORConf and keep the event accessible to all members of the community.
Professional tickets are £ 250 and can by bought here via PayPal or by email.
Professional ticket holders will receive some swag and a special name badge as a thank you.
We expect all participants of ORConf to follow the FOSSi Foundation code of conduct.
We encourage anyone involved in the open source semiconductor engineering space to come along and give share your work or experience.
This year we're offering lightning talk and 15-minute speaking slots, with the choice of opting in to be considered for an extended slot of 30-40 minutes. We are intentionally reducing the standard speaking slot length this year to ensure we can accomodate all of the exceptional talk submissions we recieve, and to maximise face-to-face time throughout the event. We encourage speakers to skip the technical deep-dive presentations and instead provide high-level introductions and overviews of what makes their work great, and prepare a poster or hardware demo for people to come and discuss details during the breaks.
So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.
We are pleased to announce Western Digital as the headline sponsor of ORConf 2019.
You can also support us with small donations via Paypal:
As is tradition at ORConf, a dinner will be arranged for the Saturday evening (28th) which all conference attendees and partners are encouraged to attend.
We are open to the sponsorship of this dinner, so please get in touch with us to find out more.
The growth of human and business interaction with technology continues to explode. At the literal heart of that technology sits a silicon core, combined with general and specific instructions and connections. The insane cost, risk, development time, necessary volumes, and limited computing demands kept the lucrative chip opportunity within reach of just a handful of companies -- focused mostly on general purpose processors. New computing needs in various power and performance dimensions have increased demand and competition for custom processors. This pressure is quietly and rapidly disrupting the processor industry. An Open source approach to processors now reduces risk and investment, with accelerated time to market, and opens the opportunity to thousands of possible custom processors. Learn about the trends, opportunities, and examples -- from smart watches to supercomputers -- as well as the global momentum of RISC-V!
Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry.
We have recently launched the CHIPS Alliance project: CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development. The organization was created to host and curate high-quality, open source hardware design relevant to the design of silicon devices. By creating a neutral and collaborative environment, CHIPS Alliance intends to share resources to lower the cost of development and accelerate the creation of more efficient and innovative chip designs – covering the span from small IoT devices to large datacenter silicon solutions.
As an independent entity, companies and individuals can work together and contribute resources to help make open source chips, complex IP blocks and system-on-a-chip (SoC) design more accessible to the market.
We will describe some of our initial projects, focused on RISC-V cores, design and design verification tools and analog IPs, as well as structure of workgroups and existing meetings in CHIPS alliance.
Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Zvonimir is Chair of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.
This talk will detail the creation of the OpenHW Group, a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. The talk will also cover the launch of the CORE-V Family of open-source RISC-V cores.
Rick O'Connor is Founder and serves as President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. The OpenHW Group Core-V Family is a series of RISC-V based open-source cores with associated processor subsystem IP, tools and software for electronic system designers.
nextpnr, a next-generation multi-architecture FPGA place-and-route tool was presented at ORConf 2018 with both iCE40 and highly experimental ECP5 support. Over the past year, we have taken the ECP5 support from proof-of-concept to production-ready, and opened up the possibility to use nextpnr to build large and complex designs. This has included augmenting the existing simulated annealing placer with a significantly faster analytical placer (HeAP), adding multi-threaded timing analysis, and adding support for the nitty-gritty hardware details needed for high-speed IO interfaces.
The end result is the capability to build large designs quickly, such as Linux-capable VexRiscv and Rocket processors with DDR3 memory and Gigabit Ethernet. A live demo of this collaborative open gateware and toolchain project will be given.
This talk will introduce some of the improvements made to nextpnr, as well as a roadmap to improved support for even bigger and better FPGAs in the future – and how you can get involved!
David is the owner of Griffith Research Ltd and a developer of open source FPGA toolchains including nextpnr and Yosys. He documented the bitstream of the Lattice ECP5 FPGAs in Project Trellis and used this to build an end-to-end open-source flow for these parts using Yosys and nextpnr.
Open source penetrates the microelectronics design, making hardware development more accessible. To leverage this effect, one needs open CAD tools, including formal verification facilities. The talk is concentrated on an experimental comparison of several open-source model checkers for Verilog modules on open benchmarks. For selected tools Verilog support and property checking facilities were evaluated on typical designs and industrial-scale modules. This talk also briefly describes Retrascope - a new open-source model checker that verifies Verilog descriptions against SVA properties. The toolkit allows analyzing of HDL descriptions, reconstructing and visualization of the underlying models and using the derived models for test generation and property checking.
Sergey Smolov is junior researcher of Programming Technology Department of Ivannikov Institute for System Programming of the Russian Academy of Sciences. He received the bachelor's degree in 2008 and master's degree in 2010 both from Moscow Institute of Physics and Technology (MIPT). His research interests include microprocessors modeling and functional verification.
VHDLTool is an opensource project founded by CNES to help people writing cleaner and safer VHDL code. It is based on several tools like:
Florent is a SOC designer at the French Space agency (CNES).
There were significant changes in LibreCores CI over the past year. Let's take a look at what's new available to hardware projects: Docker images for EDA tools, new Jenkins server bundles, and SaaS for projects. And how was Google Summer of Code in LibreCores CI this year?
Oleg is an R&D and Automation engineer with Hardware/Embedded background. He contributes to the LibreCores project and works on the continuous integration service there. He is also a Jenkins core maintainer and a leader of Hardware/EDA SIG there. Nowadays Oleg lives in Switzerland and works for CloudBees.
The PULP project has been actively working on new ideas over the summer. In this talk I will briefly introduce the latest projects and chips the group has worked on. PULP project is committed to release all proven hardware with a permissive open source license (Solderpad) and we hope that ideas that we developed in the latest chips will also prove themselves useful and can become part of our releases.
Frank has been involved in the PULP project since the beginning in 2013. His background is in digital IC design but these days he is only allowed to talk about the projects, leaving the real work to younger (and more capable) colleagues
RudolV is yet another 5-stage in-order RISC-V core. In contrast to other implementations it focuses on timing predictability by avoiding speculative components like out-of-order execution, dynamic branch prediction or caches. Without affecting the predictability, techniques like instruction fusion, in-order dual issue and decoupled fetching can improve its throughput.
Jörg Mische is a researcher on real-time capable manycore systems and networks-on-chip. He presented the Reduced Complexity ManyCore (RC/MC) and its predictable PaterNoster NoC at earlier ORCONFs. After leaving university, he is now a freelancer in the area of real-time FPGA systems.
In a complex Verilog design, it can be difficult to relate timing reports for critical paths back to the the source code because of the way a design is flattened and optimised in a physical design flow. Being able to quickly correspond a timing path to the source code is useful in determining causes and potential fixes. This talk describes a simple command-line tool to do this. It uses a modified version of Verilator to obtain a netlist from Verilog source code and provides options to query paths and cones of logic by specifying start, end and through points in the design, similar to what you find with EDA tooling.
Jamie Hanlon works as an Engineer at Graphcore in Bristol (UK), a company building silicon processors for machine intelligence. He is part of the Silicon team, working on the logical and physical design of the a processor, replicated thousands of time over the chip. Previously he has worked on compiler and toolchain software, specifically LLVM, and completed a PhD at the University of Bristol in computer architecture.
GNU poke is a new interactive editor for binary data. Not limited to editing basic entities such as bits and bytes, it provides a full-fledged procedural, interactive programming language designed to describe data structures and to operate on them.
GNU poke is useful in many domains. It is very well suited to aid in the development of programs that operate on binary files, such as assemblers and linkers. It is also good for the fast development of prototypes for programs like linkers, compressors or filters, and it provides a convenient foundation to write other utilities such as diff and patch tools for binary files. I reckon GNU poke could be useful for people working on the software stack for open source hardware systems.
First I will introduce the program and show what it does: from simple bits/bytes editing to user-defined structures and then, very very quickly due to time limitations, will cover how to describe user data, which is to say the art of writing "pickles".
Jose E. Marchesi is a GNU hacker and maintainer. Currently making a life as the teach lead of the Oracle Toolchain Team.
Gisselquist Technology, LLC, has recently developed a set of formal properties for verifying both AXI and AXI-lite interactions. The properties were then applied to many open source projects. In this talk, Dr. Gisselquist will discuss both how the property set works and some of the bugs he has found using it.
Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His most recent work has involved formally verifying bus components using SymbiYosys.
The Chips4Maker service was first brought forward on ORConf two years ago. At that time it was mostly a dream. In the mean time much progress has been made on the design flow front and a few test tape-outs have been performed. The progress will be reported during this presentation.
If moon, earth and sun are forming the right constellation even some more concrete announcements may be made on the Chips4Makers service.
Staf Verhaegen is an open source software enthusiast that is dreaming of open source driving hardware innovation as it did for software.
With a software background I stumbled in the hardware 'programming' languages beginning of this decade. Since the beginning I had a love/hate relationship with the common RTL languages at best. In the beginning I thought it was just the normal rookie feeling and some persistence would solve it. After almost a decade I am convinced some fundamental shortcomings in the common RTL languages are holding back hardware development productivity and the usability by non-experts like makers.
There is hope though, as I will also highlight some recent developments which in my opinion are a big step in the right direction.
Encrypted Verilog is unusable to open source tools like Verilator. Beyond that, the Verilog encryption scheme is basically worthless. See https://acmccs.github.io/papers/p1533-chhotarayA.pdf for futher details. Or if you prefer more practical evidence, spend a little while researching actual attacks on encrypted RTL.
This project is a proof of concept for a utility which would use Verilator to compile a protected Verilog module into a DPI-accessible shared object. While the compiled object could be analyzed, this approach provides little to no opportunity for the plaintext Verilog to be exposed.
Todd Strader is an engineer at Hudson River Trading and is involved with the Verilator project
This is a talk about why I love to use cocotb for my day-to-day verification tasks, and I'll briefly discuss a couple neat uses I've found for it, and how it fits into our development and verification flow.
Julius is a digital design engineer at Morse Micro, a startup based in Sydney, Australia, making mixed-signal WiFi chips. He is also a founding director of the FOSSi Foundation and a lapsed contributor to the OpenRISC project.
Come find out the current status of Xilinx Artix 7 support in the SymbiFlow project.
Tim is the founder of TimVideos and is currently heavily involved with the development of the SymbiFlow project.
TerosHDL (Twitter) is an open source project focused in the development and integration of EDA tools (ghdl, VUnit...) in an IDE. It is currently based on Atom, but in the future it will be extended to other code editors such as Visual Studio Code.
The goal of TerosHDL is bringing all facilities of software code tools to the HDL development: linter, code completion, simulators management, automate documentation, snippets. https://youtu.be/tgr1KGIitIQ.
We will introduce TerosHDL 2.0 with multiple features. In the new release the architecture has been completely rebuild in order to support more tools, reduce some dependencies and clarify the code. Some of the new features include Verilog support, additional simulators: Verilator, Icarus, additional tools like cocotb, Edalize, a linter and more beautiful documentation.
Ismael Perez is an FPGA engineer who usually use open source tools at work. When the homemade automation scripts started to be a just a bit serious he started TerosHDL project with some coworkers to ease their development task and integrate different tools.
Carlos Alberto is passionate about open source. He works in high performance and low latency systems with FPGA. He is interested in implementing software quality methodologies in HDL languages: code coverage, continuous integration... He sais that hw can be effective, scalable and reliable like sw!
Alfredo Sáez is a software engineer who has worked from backend to frontend. He is a truly enthusiast of development tools that help us to code better. And when he discovered that HDL mates don't have so many facilities as SW developers, he decided to join TerosHDL team!
Last year, Symbiotic EDA announced ASICone, an experiment to tape-out an entire ASIC with a RISC-V 32bit processor, using only open source tools on X-Fab 180nm COMS 3.3V. As expected, ASICone had been a very difficult project. The team around Prof. Elkim Roa (OnChip) believes that they have found some of the most important gaps between a typical tape-out (with commercial EDA tools) and a tape-out with open-source tools. Taking this into account, in this talk, team member Luis Rueda will present the status of ASICone: what have been done and achieved so far, what have been the learning's, what is needed to close the feature gaps in the current available open source ASIC toolchain and what should be the next steps.
Luis E. Rueda G. is a PhD student and professor at Universidad Industrial de Santander (Colombia). His current research focuses in analog accelerators for machine learning system-on-edge applications. Luis did his master of science in TU Delft (the Netherlands), and in the past, he worked in projects for NXP (the Netherlands), IMEC (Belgium) and Freescale (Brazil), mainly in mixed-signal and analog IC design. Luis is also part of the OnChip group, responsible for Onchip-V, the world's first open source RISC-V-based 32-bit microcontroller (2016), where he was in charge of the analog IP blocks design.
In June we announced Embench™ (for Embedded Benchmark), a benchmark for embedded IoT devices created by experts from both academia and industry. We first looked at past benchmark efforts to try to incorporate their good ideas and to avoid their mistakes, and drew the following seven lessons:
Our plan is to follow “Agile Benchmark Development” by bringing out an initial 0.5 version for evaluation and feedback, with a 1.0 version to be released after a few iterations of preliminary Embench versions (0.5, 0.6, 0.7,...) to debug both the suite and the ground rules. We initially aim to evaluate microcontrollers that support ≤64KiB of code and read only data—which would typically be stored in Flash or ROM—and ≤16KiB of data.
In this talk we describe Embench 0.5. Unlike the popular Dhrystone and CoreMark benchmarks that are single synthetic programs, Embench 0.5 suite has 20 real programs. They do little or no floating point computation, but some are branch intensive, some memory intensive, and some integer compute intensive. Like SPEC, the single performance number that people will promote is the geometric mean of performance relative to a reference platform of the 20 programs plus the geometric standard deviation to indicate the significance of differences between processors. Novel features of Embench include reporting code size as well as program performance and to measure interrupt latency and context switching. These novel features play an important role in embedded computing but have not yet appeared in embedded benchmarks. The Free and Open Source Silicon (FOSSi) Foundation organization is the official sponsor of Embench. The Embench organizing committee now has more than 10 volunteers to evolve the benchmark.
In addition to announcing Embench 0.5, we will demonstrate its value by contrasting its performance evaluation of several embedded systems to Dhrystone and CoreMark.
Our hope is that henceforth is that publications of performance for embedded computers will include Embench along with Dhrystone and CoreMark, and that Embench will eventually retire these much older, single, synthetic benchmarks to the dustbin of history.
Jeremy Bennett is Vice-chair and convener of the Embench working group, which is developing a new set of benchmarks for Embedded systems.
Due to recent work by Tristan Gingold and some contributions from Pepijn de Vos, it is now possible to use GHDL for synthesis with Yosys. Furthermore, improvements in support for PSL and VHDL-2008 make it possible to use GHDL with SymbiYosys for formal verification. This talk will give an overview of the state of open source VHDL synthesis, and introduce formal verification using these tools.
Pepijn is a software developer and electrical engineer who got in touch with FPGA development during his electrical engineering bachelor at the University of Twente. Pepijn prefers vim and makefiles over clunky commercial EDA tools, and is trying to make his future career more pleasant by contributing to open source tools.
verilog-to-routing's P&R tool VPR, which is used in SymbiFlow's Artix 7 flow, can accept FPGA architecture and routing resources as file inputs. I have worked on the speed and correctness of this process as part of this year's GSoC.
Fahrican is GSoC'2019 student for SymbiFlow.
The rise of open hardware pushed by open architectures such as RISC-V must be accompanied by open tool suites making it accessible to the largest number. Today, two distinct profiles are required to produce an electronic device: hardware designers and software developers. Hardware designers often work on close-source, expensive tool suites with only a small degree of freedom, to produce a suitable hardware prototype. Once low-level software produced (kernel, drivers...) from the hardware specification, software developers then use the prototype as a support for their developments and testing, with other tools. This long, sequential process could be dramatically shortened by using a unique collaborative tool, centered around a software representation of the hardware: a virtual platform.
In this talk, we will present Hiventive's multi-simulator virtual platform engine running a RISC-V virtual platform embedding a Linux distribution. Compare to existing solutions, Hiventive's multi-simulator doesn't focus on only one simulator, but instead take advantage of existing great simulators like QEMU, GEM5, and more.
Benjamin Barrois is the CTO and one of the co-founders of Hiventive, a young startup aiming to revolutionize the way electronics products are designed. He joined the adventure after getting a PhD about low-power computer arithmetics.
A Globally Asynchronous, Locally Synchronous (GALS) circuit consists of a set of locally synchronous modules with isolated clock domains communicating with each other via asynchronous wrappers. Because of the reduced EM interference and lower power requirements, the GALS approach is one of the most promising techniques for building the next generation of System-on-Chip (SoC) devices, being specially fitted for Network-on-Chip (NoC) based architectures.
Obscurity and lack of proper fine-grained control in proprietary toolchains has historically supposed a very limiting factor for any asynchronous logic design research effort related with FPGAs. In this talk, we will demonstrate with a reproducible demo how the basic asynchronous NoC circuitry involved in a GALS based SoC can be efficiently built by using the Free & Open Source libraries from the AsyncArt project and a 100% FLOSS toolchain for FPGAs.
Javier D. Garcia-Lasheras is a researcher and entrepreneur specialized in high-performance Cyber-Physical Systems. He is an early pioneer on implementing asynchronous NoCs on FPGAs and ASICs and he created the AsyncArt project in 2012 to share his previous research on the topic. In addition, he has made other contributions to the Free & Open Source community related with software, as a participant in Linux Foundation's Yocto Project, and with hardware, as a former project manager for CERN's HDLMake tool.
SCR1 is an open-source MCU-class RISC-V core for deeply embedded applications and accelerator control, developed and maintained by Syntacore. Over the three years of its existence, the processor has found significant traction both in industry and in academia around the world.
in our brief presentation, we will talk about the SCR1 key features and the latest updates, as well as invite you to our demo, where we show the use of SCR1 both for educational purposes and for commercial projects.
Ekaterina Berezina is a Senior HW Engineer at Syntacore, where she contributes to the SCRx core family development and maintenance. Ekaterina has more than 6 years of experience in CPU IP development including architecture and microarchitecture definition, RTL design, testing and verification, area/timing/power optimization for ASIC and FPGA. She received her Master’s degree in Computer Science at Saint-Petersburg ITMO University and teaches Computer Architecture classes there.
Ivan Piatak is an ASIC design engineer at Syntacore. He received his MS and PhD degrees from the Peter the Great St.Petersburg Polytechnic University where he also currently serves in the research assistant position at the Higher school of applied physics and space technologies. His research interests are in the low power data acquisition methods with a specific focus on the digitally-assisted pipelined ADCs design. At Syntacore, he is responsible for the ASIC digital backend and layout in the customer projects, and also contributes to FPGA prototyping."
Barcelona Supercomputer Center - Centro Nacional de Supercomputación (BSC-CNS) is the leading supercomputing center in Spain. It houses MareNostrum, one of the most powerful supercomputers in Europe, and is a hosting member of the PRACE European distributed supercomputing infrastructure. The mission of BSC is to research, develop, and manage information technologies to facilitate scientific progress. We have a long history of developing software stacks for HPC. Over the years, We have released many open source tools for instrumentation, visualization, and analysis of software and architectures, but RTL design has been a research area quite limited until now. The growth of an Open Digital design ecosystem has enabled BSC to explore computer architecture at a deeper level, closing the gap between academia and industry.
Last May BSC, along Universitat Politècnica de Barcelona (UPC), Centro Nacional de Microelectrònica (CNM) and Centro de Investigación en Computación del Instituto Politécnico Nacional de México (CIC) summited for manufacturing the preDRAC processor, our first RISC-V ASIC design. In this presentation, We will talk about the compromise of BSC with RISC-V, show an overview of preDRAC, and describe the role of Open Source IP and tools in the project.
Guillem Cabo is a research engineer at BSC-CNS. He was involved in the tape out of preDRAC. He is currently working on RTL design, mainly designing and integrating control mechanisms for real-time multi-core processors in several H2020 projects, at the CAOS group.
Andrew Katz is a partner at Moorcrofts LLP, a boutique law firm in England's Thames Valley and advises a wide range of businesses on free and open source related issues. He has lectured and published widely on the subject and is a founder editor of the International Free and Open Source Software Law Review. Before becoming a solicitor, he trained as a barrister, and moonlighted as a programmer during his studies at Bar School, programming in Turbo Pascal. He has released software under the GPL.
An update on all that is happening this year with OpenRISC. I would like to go over the interesting things happening this year in OpenRISC. LibreCores continuous integration setup for IP cores. Releasing the Marocchino CPU. Incorporating proposals into and publishing OpenRISC spec 1.3. Working on the glibc port and finding some interesting bugs.
Stafford is an software engineer as SMBC Nikko Japan working on algorithmic trading systems. He has been working on and maintaining OpenRISC for the better part of 5 years.
cocotb is a COroutine based COsimulation TestBench environment for verifying VHDL/Verilog RTL using Python. It is an alternative to UVM and other verification approaches, and has been gaining an increasing number of followers over the last years.
In 2019, we already released cocotb 1.1 and 1.2, and more releases are upcoming. This talk will show what's new and exciting in cocotb land, and outline areas where we're looking for more contributors!
Philipp is an engineer at lowRISC doing Open Source hardware design, and a director at FOSSi Foundation. He has been a long-time open source enthusiast, working on software, hardware, automation, and outreach.
When debugging C applications, whilst the debugger handles high level operations, it abstracts and offloads lower level operations to a debug server which is responsible for controlling the process or hardware. The debug server is capable of very simple operations, such as reading/writing registers and memory, starting and single-stepping the processor and reporting back when the processor halts. The two communicate with each other using a very simple text based serial protocol.
GDB has long been served by a number of debug server options, for Linux class systems the gdbserver application provides this functionality, and for embedded systems the gdbserver built into OpenOCD is commonly used, but support for some targets (such as RTL simulation) we can do better. In this talk, we present a new open source debug server that supports these usecases. It is capable of controlling the simplest hardware, through to complex multicore heterogenous architectures. I present the aims of this project and what we want to achieve as this progresses.
Simon is a tool chain engineer at Embecosm, at which he focuses on the LLVM compiler and tools for debugging embedded applications.
VPR, an open source Place&Route tool developed primarily by the University of Toronto, describes the FPGA devices architecture using model and pb_type XML files . The XML files can be really complex depending on the device architecture.
V2X is an open source tool for generating FPGA architecture description XML files from Verilog models. The models can be reused as device simulation modes.
Currently V2X supports the following features:
Karol Gugala is Engineering Manager at Antmicro, where he is working with open source in various contexts - primarily FPGA and embedded software. Open source enthusiast - involved in a wide variety of FOSS projects.
BlackEdge is the new myStorm proposed FPGA OpenSource Hardware roadmap for embedded heterogenous development systems, we take a look at the standard and a peek under the open hardware kimono to see what's coming down the road project wise.
Alan Wood (@folkonlogy) is a hardware and software engineer, specialising in heterogeneous embedded systems, machine vision/learning and dev systems
This story is about the new improvements in LibreCores.org for assisting discoverability of new open-source IP cores, presenting the analysis of project quality of published LibreCores and features for increasing user interaction.
Amitosh is a contributor to LibreCores.org, first getting involved in 2017 as his Google Summer of Code project. He has consistently been a part since then assisting with the development and maintenance of the project. Presently, he is a software engineer at GoPay, the payments division of SE Asian "super-app" Gojek.
Having FPGAs available in the data center presents enormous potential for new and exciting compute models. But, for this emerging ecosystem to thrive, we need infrastructure to develop custom hardware accelerators for these platforms and integrate them with web applications and cloud infrastructure. The 1st CLaaS (Custom Logic as a Service) Framework brings cloud FPGAs within reach of the open-source community, startups, and everyone.
1st CLaaS provides an end-to-end solution for streaming data to and from custom logic using WebSockets. It provides infrastructure for development, provisioning, and deployment of custom FPGA logic as a microservice, significantly reducing the development overhead of integrating cloud FPGAs for acceleration of web and cloud applications.
This talk will introduce the framework and some of its recent improvements as well as the impact it could have on open-source silicon.
Ákos Hadnagy is master’s student at TU Delft. He became involved in the project through Google Summer of Code, returning for the second year after contributing to WARP-V last summer.
His interests include heterogenous and reconfigurable computing and FPGA and hardware development.
OmniXtend cache coherence protocol is open source protocol based on mapping of TileLink cache coherence messages on the top of standard Ethernet 802.3 L1 frames. The protocol takes advantage of availability of programmable Ethernet switches - using P4 programming language.
We have recently published the specification of OmniXtend, and open-sourced P4 code for the programmable Barefoot Networks switch. We will present the design philosophy of OmniXtend, present the latency measurement in the implemented system and show of first 8-core RISC-V cluster consisting of two RISC-V 4-core nodes, connected via OmniXtend switch.
Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors.
He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.
Zvonimir is Chairman of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.
Renode has been available as a permissively licensed desktop simulation framework for (unmodified) software development and HW/SW co-development in complex systems - including multi-node, heterogeneous multi-core and multi-architecture ones - for some years now, gaining momentum especially with the advent of RISC-V and open ISAs in general.
Besides a host of awesome recent developments in version 1.8 such as physical FPGA and Verilator co-simulation, enhanced multi-core debug, support for many new RISC-V platforms, Renode has also some big changes to announce.
The collaborative nature of virtual development - with features such as state saving, event storing/replaying, synchronous debug of multi-node environments and simply being able to share your work with colleagues using a bunch of files - is best experienced in a cloud environment, where resources can be truly shared and easily scaled. In this talk, we’re announcing the Renode Cloud Environment, an open source design, testing and CI system that builds on and integrates with Renode.
Michael is VP Business Development at Antmicro and one of the creators of Renode. With a background in both computer science and the humanities, he is an ardent believer in using open source to advance entire industries. Michael is vice-chair of Marketing in the RISC-V Foundation and Chair of Marketing and Outreach in CHIPS Alliance.
The RISC-V ISA specifies a register file of 31 registers of 32 bits each. This project aims to eliminate this requirement by memory mapping the register file into the same memory as used for program and data. The resulting architectural state consists of only the program counter, with instructions that read arguments and write results to memory over multiple cycles. This is reminiscent of old processors such as the 6502. As an optimization, the internal state can be considered as a register-file cache, leading to some interesting design considerations.
David Hossack is a design engineer at Analog Devices in Boston MA, USA. This project occupies some of his limited spare time.
DUH is an opensource data format designed to capture information about reusable HW components. It provides a standard way of capturing: ports, bus interfaces, memory maps, registers, generator parameters, clocks, resets, etc. DUH format supported with a variety of tools.
Import tools help to import available information from Verilog, IPXACT, SystemRDL sources. Inference tools do the guesswork finding standard bus interfaces. DUH document can be opened and inspected in the web browser. DUH document has a standard JSON schema and can be validated. DUH export tools provide Verilog, IPXACT, Chisel-Scala output. The goal of DUH project is to make HW IP more reusable and enable more SoC automation tools.
Aliaksei Chapyzhenka is an engineer at SiFive Inc., author of the WaveDrom project and OSS contributor since 2011.
Rocket Chip is an open-source RISC-V processor-complex generator that comprises the Rocket microarchitecture and TileLink interconnect generators. It has been used in over 20 tape outs by UC Berkeley alone, and is an important piece of the SiFive FE310 (HiFive 1) embedded SoC as well as the Linux-capable FU540 SoC (HiFive Unleashed). A common question in the open-source community is “How do I integrate Rocket Chip into my SoC”. This talk is an introduction to the use of Rocket Chip and how one might onboard a Verilog IP into a Rocket Chip SoC.
Jack Koenig is a Staff Engineer at SiFive. He maintains the Chisel and FIRRTL projects in addition to working on tooling for parameterized generators like Rocket Chip.
Microwatt is a simple Open POWER soft processor released on github in late August. It grew out of a desire to show something interesting at a recent announcement by IBM regarding the opening up of the POWER ISA.
By the time of the conference, it will have been in the open for just over a month. This talk will detail a bit of the history behind Microwatt, recent progress, some of the challenges as well as future plans.
Anton Blanchard works at IBM where he spends his time on Linux and Open Source software, and very recently Open Source hardware.