ORConf 2017 was held from September 8th to 10th in Hebden Bridge, England.
We were pleased to be part of this year's Wuthering Bytes Festival of Technology.
A big thank you to all who attended, our sponsors, and our assistants during the event.
Recordings of talks will be posted on this site when they're ready, a big thank you to Simon Cook for filming and editing the presentations again this year.
ORConf is an open source digital design and embedded systems conference, covering areas of electronics from the transistor level up to Linux user space and beyond. Expect presentations and discussion on free and open source IP projects, implementations on FPGA and in silicon, verification, EDA tools, licensing and embedded software, to name a few.
The conference is free to attend, and we invite anyone with an interest in the field to participate by presenting or just joining us for the event. That means we're also looking for sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!
The conference will run from about 12:30PM on Friday until around 3PM on the Sunday, permitting people to travel on the first and last day of the event and not miss any sessions.
The running order can be found here.
Below, in no particular order, are summaries of the presentations which will be made at ORConf 2017.
In this presentation, the scaling capabilities of "Many-Core" frameworks are discussed through the demonstration of a parallelized software renderer and massively multi-player online game server.
Michael is a seasoned mobile developer and Linux enthusiast who has taken an active role in the promotion of Free Hardware. Since the last ORConf, he's spent research efforts focused on exploring the possibilities of many-core development via the OpenPiton framework.
An update on the progress of the OpTiMSoC multicore SoC project.
The free and open Programming, Design and Verification Language (PDVL) is presented. It comes with an open source EDA framework for PDVL-to-Verilog conversion and PDVL simulation.
Presenter: Tobias Strauch of EDAptix
System Hyper Pipelining (SHP) is a design transformation process. It converts for instance single CPUs into multithreaded CPU. Individual threads can be stalled, bypassed and reordered and can therefore be executed at different speeds. SHP is ideal for FPGAs. An open source project based on an RV32IMAC, the ARTY board and the Arduino IDE is presented during the conference.
Presenter: Tobias Strauch of EDAptix
Kunal will talk about a novel technique of building open-source hardware community using adaptive and adaptable learning mode with open-source EDA tools. The gap confronted here is shortfall of guidelines and support systems to use these tools, and one architecture that connects complete design to all tools. VSD has been attempting to fill this gap by blending the learning and practicing methods through online video courses with the goal of building a large community across the globe who are designing and innovating using open-source tools.
Presenter: Kunal Promode Ghosh of VSD
An automated C-to-GDS flow using open-source EDA tools for medium-sized SOC design and implementation
A poster presentation on a complete C to GDS flow using open source tools demonstrated on a multi-million gate design.
Presenter: Kunal Promode Ghosh of VSD
PULP is a RISC-V based multi-core computing platform targeting the requirements of a growing number of end-node Internet of Things (IoT) applications. PULP hardware and software are open-source with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.
The goal of this talk is to update the ORConf community about the recent developements on PULP including new chips, demos, application boards, software tools and the announced open source release of the PULPinoV2 system.
Presenter: Davide Rossi
Davide Rossi is an assistant professor at the department of Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.
One year ago at ORConf 2016 we announced the work on LibreCores CI - a continuous integration service for projects being hosted on LibreCores. During the last year we made some progress on this front, and we would like to talk about the current project status.
We will show show the project has evolved and present several examples and success stories. Then we will have an open discussion about the system requirements and beta testing.
Stefan is a curious developer and has been involved in the OpenRISC project for many years and is contributor to several other open source projects around SoC design. He is a director at the FOSSi Foundation, where he works on many projects including Continuous Integration prototyping for OpTiMSoC in LibreCores CI.
Oleg is an engineer with R&D and automation background in the embedded processor design area. He is a core team member in the Jenkins open-source project and a newbie contributor to hardware/EDA projects. Oleg is also a major contributor to the FOSSi Foundation's LibreCores project, and the Jenkins-based LibreCores CI work in particular.
The past year has seen increased focus by the FOSSi Foundation's licensing committee on coming up with a copyleft licence which is appropriate for HDL. This presentation will discuss a new revision of the CERN OHL licence which addresses, among others, applicability to HDL designs.
Andrew Katz is a partner at Moorcrofts LLP, a boutique law firm in England's Thames Valley and advises a wide range of businesses on free and open source related issues. He has lectured and published widely on the subject and is a founder editor of the International Free and Open Source Software Law Review. Before becoming a solicitor, he trained as a barrister, and moonlighted as a programmer during his studies at Bar School, programming in Turbo Pascal. He has released software under the GPL.
Placing a CPU into a new environment can be a daunting task. Components need to be selected, resources allocated, addresses given, interrupts assigned, and peripherals configured--not only in RTL but also for all of the software support. The problem with this approach to designing hardware is that it works very well for one-off solutions, but not for quickly creating generic solutions to new problems. This is where AutoFPGA comes in.
Given a set of components, it builds the boiler plate files, the top level and main design files, the Wishbone interconnect, and the software header files necessary for software support within that design. As a result, I can reconfigure a project with new hardware in a matter of minutes, rather than the days it took before.
Dr. Gisselquist is the lead engineer and owner of Gisselquist Technology, LLC, a services based company focused on providing superior Computer Engineering and Signal Processing services to our customers. Dr. Gisselquist has an M.S. in Computer Engineering and an Ph.D. in Electrical Engineering from the U.S. Air Force Institute of Technology. His current work has been focused on the ZipCPU, and the environment, toolsuite, and peripherals necessary to support both it and any end-user applications.
When I last presented the ZipCPU, it had no 8-bit byte support. This and several other things have now changed with the CPU. This lightening talk will present the current state of the ZipCPU project.
Presenter: Dan Gisselquist
While some claim to write bug-free software (once it compiles), most of us (voluntarily or not) rely on debugging tools during software development. On a regular desktop PC, the job is usually done by firing up a GDB instance. However, things get a bit more complicated when software runs on an embedded system. A number of challenges arises: remote debugging must be supported, non-intrusive debugging techniques are needed, and all of that with minimal cost to the final chip.
The Open SoC Debug (OSD) project aims to provide infrastructure to enable SoCs to be debuggable. First of all, OSD is a specification of a debug and trace system. The specification describes an architecture and infrastructure components which are essential in a debug and trace system. In addition, OSD comes with a reference implementation of both hardware components to be added to a SoC, and a software implementation which runs on a host PC and connects the user to the chip when debugging.
In this talk, I'll give an overview of Open SoC Debug, revisit what happened in the project since the last ORConf, and given an outlook on what's up next.
For as long as he can type, Philipp has been interested in software development. Being a real 'full stack' developer, his interests range from hardware design to web development. Making things easier to understand is a recurrent theme in his work. As developer of the LibreCores web site, he works on making digital hardware projects more discoverable. And by adding debug and trace support to SoCs, software development becomes easier on these devices.
Philipp is active in the FOSS community and currently serves director of the FOSSi Foundation. He lives and works close to the alps in Munich, Germany.
LibreCores.org is the place to go to when looking for digital hardware projects. In this talk I'll give an overview of the current status, what happened since the the launch at last year's ORConf, and what the future plans are.
Bootstrapping open source low-volume ASICs.
Presenter: Staf Verhaegen
Staf is a long time open source proponent and developer - with an interest in Linux, Python, AROS, etc. - that also would like to get that spirit in the ASIC world.
The project’s goal is to reimagine the Electronic Delay Storage Automatic Calculator (EDSAC), a computer built by Maurice Wilkes in 1949, on modern hardware, with the ultimate objective to make the historic computer accessible to and reproducible by a new generation of computer architects and engineers.
Investigating the evolution of computing techniques gives architects and engineers context to modern concepts of computer architecture, organisation and design.
I am an undergraduate pursuing Bachelors in Electrical Engineering at the Indian Institute of Technology Patna. My academic interests are in the hardware domain, especially computer architecture and organisation, digital design and embedded systems.
The openness of the RISC-V ISA has enabled the development of many open-source RISC-V cores with varying capabilities. Choosing an implementation that meets given requirements can be done to some extent by comparing specifications and other attributes of the cores, but any decision must be based on actual testing. Using Verilator to generate cycle-accurate models enables rapid development of testing platforms.
This talk provides a report of our experience bringing up cycle-accurate models of two cores in particular, RI5CY from the PuLP project, and Clifford Wolf's PicoRV32. For testing, a software ecosystem consisting of a compiler, binary utilities, debugger, and an interface between the model and debugger accompanies the Verilator model.
To compare the cores, we used the GCC test suite and the RISC-V ISA test suite for measuring correctness, and the Bristol/Embecosm Embedded Benchmark Suite (BEEBS) to compare performance. All code and scripts used for the implementation are open-source, and can be re-used by others who wish to do similar exercises with other RISC-V cores.
Dr Markall holds an MSc and PhD in Computer Science from Imperial College, London, where his doctoral research was on compiler frameworks for implementing PDE solvers.
For an FPGA design we all know that the architecture – all the way from the top to the micro architecture – is critical for both the FPGA quality and the development time. It should really be obvious that this also applies to the testbench.
Most FPGA designs are split into stand-alone modules – for instance for each of the FPGA external interfaces. In VHDL these modules are VHDL entities (components), and they are normally accessed from a CPU via a more or less standardised register interface, which acts as an abstraction layer. This abstraction allows a safe and very efficient control of the complete FPGA.
It becomes clear that this approach should also be used for the verification environment - to simplify the testbench architecture and the control of the interfaces. This way the verification structure will mirror the design structure, allowing the best possible overview, readability, maintainability and reuse.
UVVM provides a very simple and powerful architecture for this – to allow designers to build their own test harness much faster than ever before – using a mix of their own and open source verification components. OSVVM may be used seamlessly with UVVM, so that Constrained Random and Functional Coverage may be combined with a great architecture and infrastructure, and controlled in an easily understandable, maintainable and reusable way.
This presentation will show you how simple this is to understand, build and control.
Espen Tallaksen is the managing director and founder of Bitvis, an independent design centre for embedded software and FPGA. He graduated from the University of Glasgow (Scotland) in 1987 and has 30 years’ experience with FPGA and ASIC development from Philips Semiconductors in Switzerland and various companies in Norway, including his earlier founded company Digitas.
During twenty years Espen has had a special interest for methodology cultivation and pragmatic efficiency and quality improvement. One result of this interest is the UVVM verification platform that is currently being used by companies world-wide. He has given many presentations and keynotes on various technical aspects of FPGA development.
For the Wuthering Bytes festival, a two and a half day event was organised to teach near beginners FPGA programming. Dubbed Chip Hack, the course included a selection of talks and tutorials to ease the participants into the FPGA world so that by the end of the first day all participants can program a UART transmitter or a receiver.
To celebrate the 60th anniversary of the BCS, during the second half of the Chip Hack course a replica of EDSAC (implemented by Hatim Kanchwala of the Indian Institute of Technology) was brought up on the FPGA boards used the day before. The boards could interface with multiple peripherals, such as the delay lines and tape reader, to educate the participants on simple computer architecture and design.
SCR1 is an open-source MCU-class RISC-V core for deeply embedded applications and accelerator control, for which Syntacore provides maintaining and best-effort support. SCR1 has competitive features and characteristics and can be configured for RV32I or RV32E base instruction set with optional M and C extensions and variety of predefined configurable features and uncore components. The core is released under the permissive Solderpad Hardware License, which is Apache 2.0 derivative with HW specifics. SCR1 is implemented in SystemVerilog, optimized for area and power, and comes with documentation, tests, verification and synthesis collateral as well as instantiation examples and open-source FPGA-based devkit. It is compatible with the current RISC-V privileged ISA v1.10 and user ISA v2.2 specifications.
Ekaterina Berezina is an RTL designer at Syntacore, and one of the developers of the SCR1 core. She has 4 years of experience in RTL development (Intel, Syntacore) and Master’s degree in Computer Science at ITMO University, Saint-Petersburg.
Vasily Varaksin is a hardware developer at Syntacore. He has 6+ years of experience in developing SoCs based on RISC-V, MIPS, ARM and E2K architectures and masters degree in Computer Science and Moscow Institute of Physics and Technology (MIPT).
At Philips Healthcare we participated in the ARTEMIS ALMARVI project . In the context of this project we studied, among others, tools and techniques to become less platform dependent when implementing high performance real-time image processing algorithms. We aim to be portable across CPU, GPU and FPGA platforms and have zoomed in especially on enablers for portability towards FPGAs.
In this presentation we will talk about our experiences with tools and techniques to achieve software to hardware portability, coming from a software algorithm description to an FPGA implementation.
We have selected the Halide domain specific language and specifically the Halide HLS framework which generates Xilinx High Level Synthesis compatible C/C++ targeting FPGAs. As well as the new SDAccel tool from Xilinx which allows us to program System On Chip FPGAs at the abstraction level of OpenCL. SDAccel also uses the Xilinx HLS tools underneath.
Several selected image processing algorithms were tested with both approaches and some extensions and optimizations were made to improve the performance and resource utilization in the HLS output.
Presenter: Steven van der Vlugt
Steven has been with Philips Healthcare Image Guided Therapy in the Netherlands, through Topic Embedded Systems, since 2014. First as an FPGA engineer working with Xilinx High Level Synthesis tools, then working on ARTEMIS ALMARVI. He was the lead engineer, researcher and designer for Philips Healthcare and Work Package leader for one of 5 technical work packages in the European project.
On an (impossible?) quest for an open source ASIC business model tainted by my open source software heritage. There is something to be learned from the successful open source business models.
Presenter: Staf Verhaegen
This presentation will give an update on recent activities of the lowRISC project and its efforts to produce a open, secure and flexible System-on-Chip. Topics include recent tagged memory improvements, Linux kernel support for tagged memory, GSoC projects, and the RISC-V LLVM backend.
Alex Bradbury (@asbradbury) is a co-founder of the lowRISC project and a researcher at the University of Cambridge Computer Laboratory where he has spent many years researching novel compilation techniques for many-core architectures. He is currently working on an upstreamed RISC-V port of LLVM. Prior to lowRISC, he was heavily involved in the Raspberry Pi project.
SMP systems with out-of-order processors provide sequentially consistent memory operations by performing speculation and delayed commit. On the other hand, implementing sequential consistency increases hardware complexity on in-order SMP systems, where even a small amount of area gain matters significantly. Thus, a low-complexity method for sequential consistency model on low-power in-order SMP systems is appealing.
In this work-in-progress talk, I will report the latest status of implementation of a lightweight sequential consistency model on lowRISC SoC with in-order Rocket processor. I will present an overview of the interconnect and cache coherency architecture of lowRISC, followed by sequential consistency features incorporated so far. I will conclude the talk with a list of remaining work and lessons learned during the work.
Presenter: Mahircan Gul
Mahircan received his MSc degree from Technical University of Kaiserslautern, focusing on processor architecture and real-time operating systems. He's currently working as a developer of computer vision/deep learning applications on FPGA/DSP platforms, and contributes to RISC-V based open source systems outside of his day job.
Kactus2 is the most widely used graphical open source IP-XACT tool for packaging and integrating IP-blocks for System-on-Chip designs. It features the complete IP-XACT design flow, e.g. Verilog/VHDL file import, component, design and configuration editors and code generators.
The presentation will cover the latest updates and future plans for Kactus2 and discuss trends in the current design tools.
Esko Pekkarinen received the MSc degree in 2013 from Tampere University of Technology (TUT) in Finland. Since then he joined the Kactus2 open source IP-XACT tool project and acts now as the chief SW architect of the project. He is currently a researcher and PhD student at TUT.
This talk will give a whirlwind overview of the recent work by RISC-V Foundation members. Which software tools are upstreamed? What is the status of debug, memory model, vector, and other specifications? How can you get involved? Attend this talk to find out.
Alex Bradbury has been involved with the RISC-V community since its inception. He is a co-founder of the lowRISC project, which is a founding member and active participant in the RISC-V Foundation.
This presentation highlights the mission and goals of efabless.com, a company devoted to community creation and development of silicon hardware intellectual property (IP). We have a web-based platform and IP marketplace and we use and develop open source tools for the design of analog, digital, and mixed-signal circuits, and complete integrated circuit chips.
We successfully ran an analog circuit design challenge early this year, and are poised for additional challenges in digital and mixed-signal domains.
Tim has been a primary staff member of efabless.com since 2016 and is responsible for development of the company's open source EDA platform.
He has been developing open-source EDA software since the early 1990s, and have run the opencircuitdesign.com website since 2003, collecting, maintaining, and developing existing tools such as Magic and IRSIM, and writing much-needed open source tools such as qflow, qrouter, and xcircuit.
Open Circuit Design is a popular repository for open-source EDA tools for custom ASIC design. While traditionally devoted to analog circuit layout and simulation, new developments in open have presented a need for open-source solutions for digital synthesis and mixed-mode simulation.
This presentation will cover recent and planned development in digital routing, static timing analysis, full chip integration, and cosimulation.
Presenter: R. Timothy Edwards
Formal hardware verification (hardware model checking) can prove that a design has a specified property. This is different from simulation, which can only demonstrate that a property holds for some concrete traces (sets of inputs). Historically only very simple properties have been provable this way, but improvements in model checkers over the last decade enable us to prove very complex design properties nowadays.
riscv-formal is a framework for formally verifying RISC-V processors directly against a formal ISA specification. (The ISA specification used in riscv-formal is itself formally verified against Spike , the official RISC-V simulator and ""golden reference"" implementation.) riscv-formal can be made to work with any existing processor design, all that is needed is to add an additional RVFI (RISC-V formal interface) trace port to the core.
riscv-formal by default uses the open source SymbiYosys toolchain to perform the formal proofs, but it should be compatible with all major HDL formal verification flows.
In this presentation I will discuss how the complex task of verifying a processor against the ISA specification is broken down into smaller verification problems in riscv-formal, how to implement RVFI, how integrate a core with riscv-formal, and what kind of bugs can be detected using our method.
Most of the proofs performed by riscv-formal are bounded proofs, i.e. it is only proven that the properties hold for the first N cycles after reset. But with a sufficiently large N we can create high confidence that in fact all relevant states can be reached within the bound of the proof and that therefore the bounded case is a sufficient proxy for the more general unbounded case. Abstractions, cut-points, and blackboxing can further help extend the effective bound of the proof. The presentation also touches on those techniques.
Presenter: Clifford Wolf of Symbiotic EDA
An update from the directors of the FOSSi Foundation on their activities, achievements since last year and future plans.
The current members of the FOSSi Foundation board of directors.
The conference will take place in Hebden Bridge, in the UK.
The Birchcliffe Centre will be open to conference attendees for dinner and drinks from 7PM. We encourage attendees to perhaps visit a local pub between the conference closing and the dinner venue opening.
The dinner will be catered by The Olive Branch which will serve Turkish and Mediterranean cuisine. There will also be a cash bar run on the night by the good folk from Slightly Foxed Brewery. The venue will close at 10PM.
RS Components are sponsors of this year's conference dinner.
Hebden Bridge is small enough to be able to walk anywhere within the town.
From Hebden Bridge railway station, follow these Google maps directions to get to the conference venue, Hebden Bridge Town Hall.
Train from Manchester Airport can be as fast as 1h15m to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
Train from Leeds Bradford Airport can be as fast as 1h30m to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
From London and the South, the train is likely to be the best option to get to Hebden Bridge. Journey times can be as fast as 3 hours from London Euston to Hebden Bridge station. See the National Rail Enquiries site for times and ticket prices for the rail journey.
The commute between Halifax and Hebden Bridge is convenient enough to make it a practical alternative to staying in Hebden Bridge.
For example, trains depart on a Friday morning about every 20 minutes and the journey takes 10-15 minutes to get to Hebden Bridge. The return services run at least once an hour in the evening, until the final service just after 11PM. Things look similar on a Saturday and Sunday (last service on a Sunday back to Halifax is slightly before 11PM).
There appears to be several taxi firms operating in and around Halifax, and fares have been quoted at around £15-20 one-way.
There are a few accommodation options available in Hebden Bridge and the nearby minster town of Halifax, West Yorkshire, which is approximately 15 minutes from Hebden Bridge by rail.
Hotels.com list a few properties in Hebden Bridge and around, such as:
- Moyles Signature B&B
- The Hare and Hounds Country Inn
- The Crown Inn
- The White Lion Hotel
- Thorncliffe B&B
- Angeldale Guest House
Airbnb list a number of properties available in Hebden Bridge during the event (as of early May).
The Hebden Bridge Hostel may have availability however it's likely to have already sold out.
Hotels.com list a few properties in Halifax and around, such as:
- The White Swan
- The Imperial Crown Hotel (close to the train station)
- Wool Merchant Hotel
- The Old Post Office
- Premier Inn (short walk to the station)
- Travelodge (a mile walk to the station)
Airbnb list a number of properties also available in and around Halifax during the event (as of early May).
The event is arranged by the conference committee of the FOSSi Foundation, and they are always looking for sponsors help to cover the costs.
Please get in touch if you'd like to be an ORConf sponsor this year.