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ORConf

The open source digital design conference

September 27th to 29th in Bordeaux, France.

Bordeaux
(c) Xellery, CC BY-SA 3.0
About

The FOSSi Foundation are pleased to announce ORConf 2019 will be taking place in beautiful Bordeaux, France over the final weekend of September, 27th to 29th, 2019.

We are currently planning the event, so check back for updates over the next month or so.


ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space.

We invite anyone with an interest in the field to join us and also consider a presentation, big or small, on your experience as a developer or a user of open source digital design projects.

ORConf remains to be free to attend thanks to each year's sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!

ORConf is organized by the Free and Open Source Silicon (FOSSi) Foundation.

Questions? Contact the organisers.

ORConf 2019: Venue | Schedule | Presentations | Dinner

Previous ORConfs: 2018 | 2017 | 2016 | 2015 | 2014 | 2013 | 2012

Registration
Free Ticket

ORConf is free to attend! We require that you register so so we know how many to expect.

Professional Ticket

Attendees who are joining us at ORConf on behalf of their company and/or can claim the conference as professional training expense are encouraged to purchase a professional ticket. These ticket sales help us provide all that we do at ORConf and keep the event accessible to all members of the community.

Professional tickets are £ 250 and can by bought here via PayPal or by email.

Professional ticket holders will receive some swag and a special name badge as a thank you.

We expect all participants of ORConf to follow the FOSSi Foundation code of conduct.

Submit a talk

We encourage anyone involved in the open source semiconductor engineering space to come along and give share your work or experience.

This year we're offering lightning talk and 15-minute speaking slots, with the choice of opting in to be considered for an extended slot of 30-40 minutes. We are intentionally reducing the standard speaking slot length this year to ensure we can accomodate all of the exceptional talk submissions we recieve, and to maximise face-to-face time throughout the event. We encourage speakers to skip the technical deep-dive presentations and instead provide high-level introductions and overviews of what makes their work great, and prepare a poster or hardware demo for people to come and discuss details during the breaks.

So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.

Venue

ORConf 2019 will be held at the ENSEIRB-MATMECA at Bordeaux INP. We'll be in amphitheatre B of their main building. Detailed directions to come.

Headline Sponsor

western digital

We are pleased to announce Western Digital as the headline sponsor of ORConf 2019.

Sponsors

Major Sponsors
OPENHW Group

Sponsors
antmicro
fossi
Donate

You can also support us with small donations via Paypal:

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Schedule
The schedule will be available closer to the event.
Saturday Night Dinner
University
(c) Olivier Aumage, CC ASA 2.0

As is tradition at ORConf, a dinner will be arranged for the Saturday evening (28th) which all conference attendees and partners are encouraged to attend.

We are open to the sponsorship of this dinner, so please get in touch with us to find out more.

Presentations


The Momentum and Opportunity of Custom, Open Source Processing

The growth of human and business interaction with technology continues to explode. At the literal heart of that technology sits a silicon core, combined with general and specific instructions and connections. The insane cost, risk, development time, necessary volumes, and limited computing demands kept the lucrative chip opportunity within reach of just a handful of companies -- focused mostly on general purpose processors. New computing needs in various power and performance dimensions have increased demand and competition for custom processors. This pressure is quietly and rapidly disrupting the processor industry. An Open source approach to processors now reduces risk and investment, with accelerated time to market, and opens the opportunity to thousands of possible custom processors. Learn about the trends, opportunities, and examples -- from smart watches to supercomputers -- as well as the global momentum of RISC-V!

Presenter: Calista Redmond

Calista Redmond is the CEO of the RISC-V Foundation with a mission to expand and engage RISC-V stakeholders, compel industry adoption, and increase visibility and opportunity for RISC-V within and beyond the Foundation. Prior to the RISC-V Foundation, Calista held a variety of roles at IBM, including Vice President of IBM Z Ecosystem where she led strategic relationships across software vendors, system integrators, business partners, developer communities, and broader engagement across the industry.

Chips Alliance Project

We have recently launched the CHIPS Alliance project: CHIPS (Common Hardware for Interfaces, Processors and Systems) Alliance harnesses the energy of open source collaboration to accelerate hardware development. The organization was created to host and curate high-quality, open source hardware design relevant to the design of silicon devices. By creating a neutral and collaborative environment, CHIPS Alliance intends to share resources to lower the cost of development and accelerate the creation of more efficient and innovative chip designs – covering the span from small IoT devices to large datacenter silicon solutions.

As an independent entity, companies and individuals can work together and contribute resources to help make open source chips, complex IP blocks and system-on-a-chip (SoC) design more accessible to the market.

We will describe some of our initial projects, focused on RISC-V cores, design and design verification tools and analog IPs, as well as structure of workgroups and existing meetings in CHIPS alliance.

Presenter: Zvonimir Z Bandic

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies , in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers. Zvonimir is Chair of CHIPS Alliance, Chair of OpenCAPI org, and Board of Directors member of RISC-V standards organization.

OpenHW Group Announces CORE-V Family of Open-Source RISC-V Cores

This talk will detail the creation of the OpenHW Group, a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate in the development of open-source cores, related IP, tools and software. The talk will also cover the launch of the CORE-V Family of open-source RISC-V cores.

Presenter: Rick O'Connor

Rick O'Connor is Founder and serves as President & CEO of the OpenHW Group a not-for-profit, global organization driven by its members and individual contributors where hardware and software designers collaborate on open source cores, related IP, tools and software projects. The OpenHW Group Core-V Family is a series of RISC-V based open-source cores with associated processor subsystem IP, tools and software for electronic system designers.

Taking nextpnr to the next level!

nextpnr, a next-generation multi-architecture FPGA place-and-route tool was presented at ORConf 2018 with both iCE40 and highly experimental ECP5 support. Over the past year, we have taken the ECP5 support from proof-of-concept to production-ready, and opened up the possibility to use nextpnr to build large and complex designs. This has included augmenting the existing simulated annealing placer with a significantly faster analytical placer (HeAP), adding multi-threaded timing analysis, and adding support for the nitty-gritty hardware details needed for high-speed IO interfaces.

The end result is the capability to build large designs quickly, such as Linux-capable VexRiscv and Rocket processors with DDR3 memory and Gigabit Ethernet. A live demo of this collaborative open gateware and toolchain project will be given.

This talk will introduce some of the improvements made to nextpnr, as well as a roadmap to improved support for even bigger and better FPGAs in the future – and how you can get involved!

Presenter: David Shah

David is an engineer at Symbiotic EDA, working on Yosys (open source synthesis) and nextpnr. He documented the bitstream of the Lattice ECP5 FPGAs in Project Trellis and used this to build an end-to-end open-source flow for these parts using Yosys and nextpnr.

Open-source model checkers: ready for industry?

Open source penetrates the microelectronics design, making hardware development more accessible. To leverage this effect, one needs open CAD tools, including formal verification facilities. The talk is concentrated on an experimental comparison of several open-source model checkers for Verilog modules on open benchmarks. For selected tools Verilog support and property checking facilities were evaluated on typical designs and industrial-scale modules. This talk also briefly describes Retrascope - a new open-source model checker that verifies Verilog descriptions against SVA properties. The toolkit allows analyzing of HDL descriptions, reconstructing and visualization of the underlying models and using the derived models for test generation and property checking.

Presenter: Sergey Smolov

Sergey Smolov is junior researcher of Programming Technology Department of Ivannikov Institute for System Programming of the Russian Academy of Sciences. He received the bachelor's degree in 2008 and master's degree in 2010 both from Moscow Institute of Physics and Technology (MIPT). His research interests include microprocessors modeling and functional verification.

Continuous VHDL inspection with open source software

VHDLTool is an opensource project founded by CNES to help people writing cleaner and safer VHDL code. It is based on several tools like:

  • VHDL Handbook toolchain: which gathers customizable VHDL good practices written in XML and a toolchain to convert it to PDF
  • Zamiacad: which is a modular and extensible platform for advanced hardware design, analysis, and research.
  • Rulechecker: which use Zamiacad to parser handbook VHDL rules
  • Sonarqube-rulechecker: which is a plugin for Sonarqube which is a GUI for debt identification and management. Sonarqube will display the errors based on VHDL handbook and evaluated by Zamiacad-Rulechecker. It will display also code coverage coming from GCOV.

Presenter: Florent Manni

Florent is a SOC designer at the French Space agency (CNES).

What's new in LibreCores CI?

There were significant changes in LibreCores CI over the past year. Let's take a look at what's new available to hardware projects: Docker images for EDA tools, new Jenkins server bundles, and SaaS for projects. And how was Google Summer of Code in LibreCores CI this year?

Presenter: Oleg Nenashev

Oleg is an R&D and Automation engineer with Hardware/Embedded background. He contributes to the LibreCores project and works on the continuous integration service there. He is also a Jenkins core maintainer and a leader of Hardware/EDA SIG there. Nowadays Oleg lives in Switzerland and works for CloudBees.

What has the PULP team been working on lately?

The PULP project has been actively working on new ideas over the summer. In this talk I will briefly introduce the latest projects and chips the group has worked on. PULP project is committed to release all proven hardware with a permissive open source license (Solderpad) and we hope that ideas that we developed in the latest chips will also prove themselves useful and can become part of our releases.

Presenter: Frank K. Gürkaynak

Frank has been involved in the PULP project since the beginning in 2013. His background is in digital IC design but these days he is only allowed to talk about the projects, leaving the real work to younger (and more capable) colleagues

RudolV: from the RISC-V SoftCPU contest to a timing predictable core

RudolV is yet another 5-stage in-order RISC-V core. In contrast to other implementations it focuses on timing predictability by avoiding speculative components like out-of-order execution, dynamic branch prediction or caches. Without affecting the predictability, techniques like instruction fusion, in-order dual issue and decoupled fetching can improve its throughput.

Presenter: Jörg Mische

Jörg Mische is a researcher on real-time capable manycore systems and networks-on-chip. He presented the Reduced Complexity ManyCore (RC/MC) and its predictable PaterNoster NoC at earlier ORCONFs. After leaving university, he is now a freelancer in the area of real-time FPGA systems.

netlist-paths: A command line tool for querying paths in a Verilog design

In a complex Verilog design, it can be difficult to relate timing reports for critical paths back to the the source code because of the way a design is flattened and optimised in a physical design flow. Being able to quickly correspond a timing path to the source code is useful in determining causes and potential fixes. This talk describes a simple command-line tool to do this. It uses a modified version of Verilator to obtain a netlist from Verilog source code and provides options to query paths and cones of logic by specifying start, end and through points in the design, similar to what you find with EDA tooling.

Presenter: Jamie Hanlon

Jamie Hanlon works as an Engineer at Graphcore in Bristol (UK), a company building silicon processors for machine intelligence. He is part of the Silicon team, working on the logical and physical design of the a processor, replicated thousands of time over the chip. Previously he has worked on compiler and toolchain software, specifically LLVM, and completed a PhD at the University of Bristol in computer architecture.

GNU poke, an extensible editor for structured binary data

GNU poke is a new interactive editor for binary data. Not limited to editing basic entities such as bits and bytes, it provides a full-fledged procedural, interactive programming language designed to describe data structures and to operate on them.

GNU poke is useful in many domains. It is very well suited to aid in the development of programs that operate on binary files, such as assemblers and linkers. It is also good for the fast development of prototypes for programs like linkers, compressors or filters, and it provides a convenient foundation to write other utilities such as diff and patch tools for binary files. I reckon GNU poke could be useful for people working on the software stack for open source hardware systems.

First I will introduce the program and show what it does: from simple bits/bytes editing to user-defined structures and then, very very quickly due to time limitations, will cover how to describe user data, which is to say the art of writing "pickles".

Presenter: Jose E. Marchesi

Jose E. Marchesi is a GNU hacker and maintainer. Currently making a life as the teach lead of the Oracle Toolchain Team.

Formally Verifying AXI Interfaces

Gisselquist Technology, LLC, has recently developed a set of formal properties for verifying both AXI and AXI-lite interactions. The properties were then applied to many open source projects. In this talk, Dr. Gisselquist will discuss both how the property set works and some of the bugs he has found using it.

Presenter: Dan Gisselquist

Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His most recent work has involved formally verifying bus components using SymbiYosys.

The state of Chips4Makers; an ASIC service for makers and hobbyists

The Chips4Maker service was first brought forward on ORConf two years ago. At that time it was mostly a dream. In the mean time much progress has been made on the design flow front and a few test tape-outs have been performed. The progress will be reported during this presentation.

If moon, earth and sun are forming the right constellation even some more concrete announcements may be made on the Chips4Makers service.

Presenter: Staf Verhaegen

Staf Verhaegen is an open source software enthusiast that is dreaming of open source driving hardware innovation as it did for software.

On a quest for the ideal HDL(s) for makers and hobbyists

With a software background I stumbled in the hardware 'programming' languages beginning of this decade. Since the beginning I had a love/hate relationship with the common RTL languages at best. In the beginning I thought it was just the normal rookie feeling and some persistence would solve it. After almost a decade I am convinced some fundamental shortcomings in the common RTL languages are holding back hardware development productivity and the usability by non-experts like makers.

There is hope though, as I will also highlight some recent developments which in my opinion are a big step in the right direction.

Presenter: Staf Verhaegen

DPI protected Verilog instead of encryption

Encrypted Verilog is unusable to open source tools like Verilator. Beyond that, the Verilog encryption scheme is basically worthless. See https://acmccs.github.io/papers/p1533-chhotarayA.pdf for futher details. Or if you prefer more practical evidence, spend a little while researching actual attacks on encrypted RTL.

This project is a proof of concept for a utility which would use Verilator to compile a protected Verilog module into a DPI-accessible shared object. While the compiled object could be analyzed, this approach provides little to no opportunity for the plaintext Verilog to be exposed.

Presenter: Todd Strader

Todd Strader is an engineer at Hudson River Trading and is involved with the Verilator project

#LocoForCoco

This is a talk about why I love to use cocotb for my day-to-day verification tasks, and I'll briefly discuss a couple neat uses I've found for it, and how it fits into our development and verification flow.

Presenter: Julius Baxter

Julius is a digital design engineer at Morse Micro, a startup based in Sydney, Australia, making mixed-signal WiFi chips. He is also a founding director of the FOSSi Foundation and a lapsed contributor to the OpenRISC project.

Status of Xilinx Artix 7 support in Symbiflow

Come find out the current status of Xilinx Artix 7 support in the SymbiFlow project.

Presenter: Tim 'mithro' Ansell

Tim is the founder of TimVideos and is currently heavily involved with the development of the SymbiFlow project.

TerosHDL: an open source IDE for FPGA developers

TerosHDL (Twitter) is an open source project focused in the development and integration of EDA tools (ghdl, VUnit...) in an IDE. It is currently based on Atom, but in the future it will be extended to other code editors such as Visual Studio Code.

The goal of TerosHDL is bringing all facilities of software code tools to the HDL development: linter, code completion, simulators management, automate documentation, snippets. https://youtu.be/tgr1KGIitIQ.

We will introduce TerosHDL 2.0 with multiple features. In the new release the architecture has been completely rebuild in order to support more tools, reduce some dependencies and clarify the code. Some of the new features include Verilog support, additional simulators: Verilator, Icarus, additional tools like cocotb, Edalize, a linter and more beautiful documentation.

Presenters: Ismael Pérez, Carlos Alberto, Alfredo Sáez

Ismael Perez is an FPGA engineer who usually use open source tools at work. When the homemade automation scripts started to be a just a bit serious he started TerosHDL project with some coworkers to ease their development task and integrate different tools.

Carlos Alberto is passionate about open source. He works in high performance and low latency systems with FPGA. He is interested in implementing software quality methodologies in HDL languages: code coverage, continuous integration... He sais that hw can be effective, scalable and reliable like sw!

Alfredo Sáez is a software engineer who has worked from backend to frontend. He is a truly enthusiast of development tools that help us to code better. And when he discovered that HDL mates don't have so many facilities as SW developers, he decided to join TerosHDL team!

ASICone, from Verilog to GDSII with open source tools only, Status and Challenges

Last year, Symbiotic EDA announced ASICone, an experiment to tape-out an entire ASIC with a RISC-V 32bit processor, using only open source tools on X-Fab 180nm COMS 3.3V. As expected, ASICone had been a very difficult project. The team around Prof. Elkim Roa (OnChip) believes that they have found some of the most important gaps between a typical tape-out (with commercial EDA tools) and a tape-out with open-source tools. Taking this into account, in this talk, team member Luis Rueda will present the status of ASICone: what have been done and achieved so far, what have been the learning's, what is needed to close the feature gaps in the current available open source ASIC toolchain and what should be the next steps.

Presenter: Luis Eduardo Rueda Guerrero

Luis E. Rueda G. is a PhD student and professor at Universidad Industrial de Santander (Colombia). His current research focuses in analog accelerators for machine learning system-on-edge applications. Luis did his master of science in TU Delft (the Netherlands), and in the past, he worked in projects for NXP (the Netherlands), IMEC (Belgium) and Freescale (Brazil), mainly in mixed-signal and analog IC design. Luis is also part of the OnChip group, responsible for Onchip-V, the world's first open source RISC-V-based 32-bit microcontroller (2016), where he was in charge of the analog IP blocks design.

Embench™ 0.5: A Free Benchmark Suite for IoT from an Academic-Industry Cooperative

In June we announced Embench™ (for Embedded Benchmark), a benchmark for embedded IoT devices created by experts from both academia and industry. We first looked at past benchmark efforts to try to incorporate their good ideas and to avoid their mistakes, and drew the following seven lessons:

  1. Embench must be free (no cost).
  2. Embench must be easy to port and run.
  3. Embench must be a suite of real programs.
  4. Embench must have a supporting organization that maintains its relevance over time.
  5. Embench must report a single summarizing performance score.
  6. Embench should report geometric mean and standard deviation as the summarizing score.
  7. Embench must involve both academia and industry.

Our plan is to follow “Agile Benchmark Development” by bringing out an initial 0.5 version for evaluation and feedback, with a 1.0 version to be released after a few iterations of preliminary Embench versions (0.5, 0.6, 0.7,...) to debug both the suite and the ground rules. We initially aim to evaluate microcontrollers that support ≤64KiB of code and read only data—which would typically be stored in Flash or ROM—and ≤16KiB of data.

In this talk we describe Embench 0.5. Unlike the popular Dhrystone and CoreMark benchmarks that are single synthetic programs, Embench 0.5 suite has 20 real programs. They do little or no floating point computation, but some are branch intensive, some memory intensive, and some integer compute intensive. Like SPEC, the single performance number that people will promote is the geometric mean of performance relative to a reference platform of the 20 programs plus the geometric standard deviation to indicate the significance of differences between processors. Novel features of Embench include reporting code size as well as program performance and to measure interrupt latency and context switching. These novel features play an important role in embedded computing but have not yet appeared in embedded benchmarks. The Free and Open Source Silicon (FOSSi) Foundation organization is the official sponsor of Embench. The Embench organizing committee now has more than 10 volunteers to evolve the benchmark.

In addition to announcing Embench 0.5, we will demonstrate its value by contrasting its performance evaluation of several embedded systems to Dhrystone and CoreMark.

Our hope is that henceforth is that publications of performance for embedded computers will include Embench along with Dhrystone and CoreMark, and that Embench will eventually retire these much older, single, synthetic benchmarks to the dustbin of history.

Presenter: Jeremy Bennett

Jeremy Bennett is Vice-chair and convener of the Embench working group, which is developing a new set of benchmarks for Embedded systems.

Open Source Formal Verification in VHDL

Due to recent work by Tristan Gingold and some contributions from Pepijn de Vos, it is now possible to use GHDL for synthesis with Yosys. Furthermore, improvements in support for PSL and VHDL-2008 make it possible to use GHDL with SymbiYosys for formal verification. This talk will give an overview of the state of open source VHDL synthesis, and introduce formal verification using these tools.

Presenter: Pepijn de Vos

Pepijn is a software developer and electrical engineer who got in touch with FPGA development during his electrical engineering bachelor at the University of Twente. Pepijn prefers vim and makefiles over clunky commercial EDA tools, and is trying to make his future career more pleasant by contributing to open source tools.

Improving VPR I/O

verilog-to-routing's P&R tool VPR, which is used in SymbiFlow's Artix 7 flow, can accept FPGA architecture and routing resources as file inputs. I have worked on the speed and correctness of this process as part of this year's GSoC.

Presenter: Fahrican Koşar

Fahrican is GSoC'2019 student for SymbiFlow.