ORConf is an annual conference for open source digital, semiconductor and embedded systems designers and users. Each year attendees are treated to an ever-impressive array of presentations from all corners of the open source hardware space.
We invite anyone with an interest in the field to join us and also consider a presentation, big or small, on your experience as a developer or a user of open source digital design projects.
ORConf remains to be free to attend thanks to each year's sponsors. Please do get in touch should you be interested in getting exposure for your company by becoming a sponsor of ORConf!
ORConf is organized by the Free and Open Source Silicon (FOSSi) Foundation.
ORConf 2018 is now over. We'd like to extend a huge thanks to everyone who attended and helped out over the weekend, and in particular to our host Marek. We'll post videos and slides of the talks in the coming weeks and contact attendees and those on the announcements list when they go up.
ORConf is free to attend! Anyhow, you must register, so that we can plan better. We expect all participants of ORCONF to follow the FOSSi Foundation code of conduct.
Registration has closed. Get in touch if you haven't registered but intend to come.
Business tickets are available if you are attending on behalf of your company. Business tickets are £ 250 and can by bought here via paypal or by email.
We encourage anybody involved in the open source semiconductor engineering space to come along and give share your work or experience. Presentations slots as short as 3 minute lightning-talks up to 30 minute talks with Q and A are available.
So if you've designed, worked on or even just used open source IP cores and/or management systems, verification IP, build flows, SoCs, simulators, synthesis tools, FPGA and ASIC implementation tools, languages and DSLs, compilers, or anything related we'd love to have you join us to share your experience.
ORConf 2018 is being hosted by the Gdansk University of Technology.
Gdańsk University of Technology, founded in 1904, is among 9 Polish universities listed by the Times Higher Education World University Rankings. The university consists of 9 faculties with nearly 23,000 students of all cycles, over 1,200 lecturers and it has more than 111,000 graduates. The Faculty of Electronics, Telecommunications and Informatics (ETI) educates about 3,500 students in five fields of studies: Informatics, Electronics and Telecommunications, Control Engineering and Robotics, Data Engineering, and Biomedical Engineering.
ETI is the largest university in Northern Poland in the area of modern technologies, employing nearly 200 researchers and lecturers. The faculty has an extensive research and didactic infrastructure at its disposal. There is also academic computer centre with one of the fastest supercomputer in Europe, as well as a state-of-the art library, anechoic chambers for acoustic research and antenna measurements, modern laboratory of industrial robots, immersive 3d visualization lab, as well as Microsoft and Cadence certified laboratories.
Welcome and Update by the FOSSi Foundation - Slides
Practical aspects of using the Open Source SCR1 core by Ekaterina Berezina - Slides
Lessons learned while formally verifying the ZipCPU by Dan Gisselquist - Slides
|09:00-09:30||Room open, coffee|
An update on SymbiFlow - a multiplatform FPGA project by Tim 'mithro' Ansell - Slides
Verilator 4.0 - Open Simulation Goes Multithreaded by Wilson Snyder - Slides
RISC-V & Renode: towards software-driven development by Michael Gielda - Slides
Cocotb update by Chris Higgs and Stu Hodgson
Python as a language for testing and code generation by Ben Reynwar - Slides
Formal Verification of WARP-V, a TL-Verilog RISC-V Core Generator by Ákos Hadnagy - Slides
Challenges and opportunities of open source licensed HW by Frank K. Gürkaynak
|09:00-09:30||Room open, coffee|
Retargeting a legacy ISA CPU core to the RISC-V architecture by Krzysztof Marcinek
Dockerizing your simulation/development environment by Gaspar Karm - Slides
Pyha: Python overlay for OOP-VHDL by Gaspar Karm
You can reach the conference venue from the airport (or any other place of the city):
If you arrive by railway: get off at Gdansk Wrzeszcz and take any of the buses mentioned above or walk.
You can also take a taxi or Uber. I recommend any of those: MyTaxi, Hallo Taxi, Neptun Taxi, As Taxi, Dajan Taxi. Avoid non corporation taxis.
If you install mobile app "Jakdojade", there is also a possibility to buy tickets for train and buses (MZKG):
There is also a 3-day ticket for city trains on SKM/PKM line (no tram or buses!) valid 72 hours. You need to go to their website, then select "Bilety strefowe" / "Bilet Trzydobowy Gdańsk — Wejherowo 28 zł" (=Zonal ticket, 3 days) choose: Discount "Bilet normalny" (=normal ticket, no discount) then you can pay by Visa/Mastercard. Probably you need to print the ticket (I did not try to buy) and you must have ID or passport with the same name as on the ticket.
Gdansk has an international airport and is served by by both major and low-cost airlines, but usefully is a hub for both Ryanair and Wizzair, making it a very affordable city to fly to from most of Europe.
There is a rail line from the aiport into the city which should make transferring from the aiport to accommodation pretty easy. There are further details on this on the Wikitravel page for Gdansk, from which most of this information is cribbed.
Gdansk is also very accessible by rail from all of Europe
Below are some accommodation options for the conference.
The Focus Hotel close to the Gdansk University of Technology (a 25 minute walk to the conference) has an offer of a special rate for ORConf visitors this year:
There is a train station for the University (Gdansk Politechnika) which should mean that anyone staying closer to town within reach of a train station should be able to access the venue relatively easily without a taxi.
Trains from Gdansk Central Station (Gdansk Glowny) run about every 10 minutes, taking 5 minutes, until about 10PM at night. So hotels near there would likely be fine as well.
RISC-V CPU Project in Western Digital: from embedded cores for SSD Flash controllers to vision of datacenter processors with open memory and accelerator interfaces.
The RISC-V Instruction Set Architecture has established itself as key driver of open source hardware projects across wide gamut of applications, such as the Internet of Things (IoT) segment, microcontrollers for a variety of traditional embedded applications, and applications requiring capability for low power operation of inference engines based on artificial neural networks.
In Western Digital, we have developed super-scalar (2-way) 9-stage pipeline mostly in-order, open-source core ECHX1, initially targeting in-house embedded Storage System on Chip applications. In this presentation, we plan to present some of the architectural details of the core, and challenges in the implementations, as well as discuss application of the core for the Flash controller. Additionally, we will explain the vision for expansion of RISC-V cores into datacenter and enterprise market.
We will also discuss open interfaces for persistent memories, such as JEDEC-standardized NVDIMM-P (Non-volatile dual inline memory module for persistent memories). We will also introduce exporting open cache-coherence protocols (such as Tilelink) over ubiquitous fabrics such as Ethernet. We plan to discuss details of the MPF4brik – memory protocol fabrik, which exposes Tilelink on the Ethernet, and allows smart switching using P4-based programmable networking. We are envisioning low-cost SMP (symmetric multiprocessing) architectures based on open standards, which will enable hyperconvergence of processing and memory in the future datacenter, and introduce new concepts, such as memory appliances.
Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies Department in a Western Digital Corporation in San Jose, California. He received his BS in electrical engineering in 1994 from the University of Belgrade, Yugoslavia, and his MS (1995) and PhD (1999) in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center distributed computing, including RISC-V based CPU technologies, in-memory compute, RDMA networking, and machine learning hardware acceleration. He has been awarded over 50 patents and has published over 50 peer-reviewed papers. Zvonimir is a member of the Board of Directors of RISC-V, OpenCAPI and Rapid-IO standards organizations.
The primary author of Verilator, the open source high-speed Verilog simulator, announces fresh for this meeting Verilator 4.0 with multithreading, and how you can get your designs' the fast(est), free simulation.
nextpnr is a retargetable FOSS FPGA place-and-route tool that is replacing arachne-pnr as place-and-route tool in the IceStorm open source iCE40 flow. It is retargetable, meaning it can be ported to other FPGA architectures easily, uses timing-driven algorithms, provides a python scripting API, supports complex placement and floorplanning constraints, and has a nice GUI. Python and GUI support are optional, which may be useful when deploying nextpnr on an embedded platform.
This presentation covers nextpnr from a user perspective, but also gives a few pointers for how to port nextpnr to new FPGA architectures.
SymbiFlow aims to be the "gcc of FPGAs", a fully open source project which supports multiple FPGAs from many different manufactures. It is currently targeting the Lattice iCE40, Lattice ECP5 and Xilinx 7 series FPGAs.
This presentation will give you an update on the current status of the project. What currently works, the future roadmap and how you can help with the project.
Tim is the founder of TimVideos and is currently heavily involved with the development of the SymbiFlow project.
Since the last ORConf I attended I have made lots of progress on getting the OpenRISC toolchain and Linux support in shape and upstreamed. I will talk about recent developments and what is on the roadmap for OpenRISC.
Stafford has been involved in Open Source since his university days in the early 2000s. Since 2015 he's been heavily involved in Open Source Hardware (FOSSi). He is now the primary maintainer for the OpenRISC Linux kernel, binutils, gdb and gcc ports.
PULP is a RISC-V based multi-core computing platform targeting the requirements of a growing number of end-node Internet of Things (IoT) applications. PULP hardware and software are open-source with the goal of supporting and boosting an innovation ecosystem focusing on ULP computing for the IoT.
In this talk the ORConf community will be updated on the recent developements in the PULP project including releases, demos, application boards, tools.
Davide Rossi is an assistant professor at the department of Electronic and Information Engineering “Guglielmo Marconi” at the University of Bologna. His research interests focus on energy efficient digital architectures in the domain of heterogeneous and reconfigurable multi and many-core systems on a chip. This includes architectures, design implementation strategies, and runtime support to address performance, energy efficiency, and reliability issues of both high end embedded platforms and ultra-low-power computing platforms targeting the IoT domain.
This presentation will cover Morse Micro's adaptation of the Berkeley/SiFive Rocket chip generator to suit their needs developing single-chip 802.11ah solutions. We will discuss the pros and cons of Chisel, Rocket's architecture, and aspects of our work in taking the Rocket project and implementing multiple deeply-embedded-class micro-controllers.
Julius is an engineer at Morse Micro, previously of Broadcom and Qualcomm where he worked as a digital design engineer developing mixed signal wireless ASICs. He was a contributor to the OpenRISC project around 2008-2013, and is a founding director of the FOSSi Foundation.
SpinalHDL is a Scala based internal DSL which allow describing and generating synthesizable VHDL/Verilog netlist.
The abstraction level of the hardware description API is close to VHDL/Verilog, but by mixing it with the general purpose programming capabilities of Scala, it offer many unconventional and powerful hardware description capabilities, which are the subject of this talk.
Bored of the hardware description languages weaknesses, I initiated the SpinalHDL project 3 years ago and currently I'm working 60% of my time as independent on the development of SpinalHDL and VexRiscv.
We use Python heavily both for both code generation (FuseSoC + FuseSoC generators), and for testing (VUnit, slvcodec, axilent, pyvivado). I'll describe our setup and briefly introduce the open-source packages that we've created to help our workflow.
Ben has working as a RTL Engineer for the last 4 years. Prior to that he spent time working on web development, software-defined radio, stay-at-home-parenting, molecular dynamics simulations, and polymer physics. The projects he mention are all packages created outside of work hours to help his work.
fusesoc_generators - For generating code using fusesoc where the generating functions have access to the generic parameters of the module.
slvcodec - Use python to create input stimulus for testing, and check simulation output. Automate creation of test benches and functions to convert to and from std_logic_vector.
axilent - Write python tests for DUT with Axi4Lite interfaces, and run the test against a simulation or against the FPGA.
Software initialization for System-On-Chip designsis essential and it must be optimal, fast and flexible furtherbe able to manage future updates in a proper way. This work presents a hardware bootloader for the OpenRISC processor where processor code is sent from a central code repository server and received through an ESP8266 WiFi module. A custom hardware module loads the code directly into system’s memory before booting the processor. This approach allows maximum wireless reconfiguration flexibility for a large number of distributed embedded systems, as needed by the IoT and related technologies.
Germán is a PhD student at the University of Seville's Department of Electronic Technology.
Open SoC Debug (OSD) is a complete solution for adding debug and trace to a SoC design. It consists of a solid specification, a software and a hardware implementation and supports tracing of CPU cores (RISC-V and OpenRISC currently), memory access (to load your software into the chip), UART emulation, and much more.
Over the last year much effort has been put into the specification and the implementation. New concepts (such as subnets) have been introduced, the software implementation has been fully rewritten and is now more robust than ever, and the hardware has gained significant test coverage (and bug fixing). In addition, run-control debugging is being worked on as part of Google Summer of Code.
This talk gives a quick overview over the Open SoC Debug architecture, and then dives into what changed over the last year.
For as long as he could type, Philipp has been interested in software development. Being a real 'full stack' developer, his interests range from hardware design to web development. Making things easier to understand is a recurrent theme in his work. As developer of the LibreCores web site, he works on making digital hardware projects more discoverable. And by adding debug and trace support to SoCs, software development becomes easier on these devices.
LibreCores helps hardware developers find the pieces of code to build their project on. Within the last year finding a suitable "IP Cores" (or LibreCores, as we like to call them) has gotten even easier and faster. With the introduction of the new search and categorization features to LibreCores developers can easily browse through similar cores, filter them and ultimately get their project done faster.
The ZipCPU is a three-year old CPU and ISA designed for low logic FPGA's. One of the challenges of any CPU design, to include the ZipCPU, is coming up with a sufficiently robust test suite to exercise all of the possible logic flows within the CPU. While formal methods can be used for this task, they are traditionally viewed as too computationally expensive to formally verify something as complex as a CPU.
Contrary to this view, the ZipCPU has now been formally verified using SymbiYosys. As a result, many bugs have been found and fixed--bugs not found previously using canned test cases. Not only that, it has also become easier to modify the CPU as necessary to achieve lower logic utilization, knowing that the formal solver will find any bugs in the updated implementations.
Dr. Gisselquist is the owner of Gisselquist Technology, LLC, a services based microbusiness focused on providing superior computer engineering and signal processing services to our customers. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering both from the U.S. Air Force Institute of Technology. His current work is focused on the ZipCPU, the environment, tool-suite, and peripherals necessary to support both it and any customer applications. He is also known for the ZipCPU blog, and has recently taken up training others in formal methods.
The presentation will briefly describe the process of retargeting the proprietary 6-stage legacy ISA CPU core to RISC-V architecture. Two BSc students were assigned for their three-month apprenticeship at ChipCraft and successfully evaluated feasibility and implemented most of User-Level ISA and partly Privileged Architecture specification. Their work will be further continued to achieve full RISC-V compliance. Our future plans are to develop a low-power single stage RISC-V twin core and release it to the open-source community under a GPL license.
Krzysztof is an Assistant Professor at Warsaw University of Technology and co-founder of WUT spin-off ChipCraft Sp z o.o.
ChipCraft is a Poland-based fabless semiconductor private company focused on providing custom world class System-on-Chip solutions for precise positioning and Telehealth/Telemedicine wearables markets. The company operations involve also design services in the field of analog, digital, mixed-signal, RF and both analog and digital backend services.
At ChipCraft and WUT Krzysztof is leading a digital research and design team focused on processor architectures, microarchitectures and instruction set extensions.
Clash is an effort to build a compiler translating Haskell to Verilog and VHDL. It supports many of Haskell's incredibly powerful constructs, allowing it to reuse much of the existing ecosystem. Clash supports powerful type inference, an interactive REPL, simulation on any target supported by GHC, abstract data types, and higher-order functions. Many hardware features are supported or under active development, such as verilog co-simulation, multiple clock domains, and bidirectional ports.
This talk provides provides a quick introduction into hardware design with Clash.
During his bachelor's at the University of Twente, Martijn came to know the creators of Clash through his involvement as a TA in the first year's functional programming course. Shortly after starting his studies abroad at Danmarks Tekniske Universitet, the creators founded QBayLogic; a company developing Clash and providing support for it in various forms. Right after graduating he joined the company and has been working there for a year. Since then, he's been an active contributor to the Clash compiler.
Project Trellis documents the bitstream and low-level architecture of Lattice ECP5 FPGAs, which combined with the SymbiFlow tools enables a full open source flow from Verilog source to a bitstream. These FPGAs contain up to 85k logic cells and a range of features including DSPs, multi-gigabit transceivers and advanced IO functionality; unlocking applications such as networking, software-defined radio, high-resolution video, and testing processors powerful enough to run Linux!
The documentation includes core features including logic, RAM and IO tiles. Work continues on both more advanced features and developing a feature-complete open toolchain for the ECP5.
This presentation will discuss what approach was taken and what tools had been developed to create useful bitstream documentation within the constraints of publicly available interfaces; a reflection on what I think worked well and what could have been improved, and how to start you on your way to documenting more FPGA architectures for open source tools - it’s not as scary as you might think!
There will also be a live hardware demonstration of the SymbiFlow open source end-to-end flow for the ECP5.
David is an engineer at Symbiotic EDA, an open source EDA startup, and a MEng student at Imperial College London; he is passionate about open toolchains for FPGAs. His work on Project Trellis began after seeing the combination of the exciting new ECP5 boards being developed, and the need for larger FPGAs with open tools to enable a wider range of projects and break down misconceptions about the limits of open source.
Previously I have worked on projects including documenting the bitstream of the iCE40 UltraPlus FPGA and adding support to it to the icestorm toolchain.
The open source Renode simulation framework was created in order to enable a software-driven approach to embedded systems development by making it easy to build simulated but binary-compatible SoCs, boards and networks by assembling reusable and object-oriented models. The rapid growth of RISC-V has given a new boost to the framework, as open, configurable CPUs have been transforming the way ASICs and FPGAs are being perceived, designed and worked with. HW/SW co-development and simulation-driven workflows are more natural in an open ISA ecosystem, and with the associated rise of open IPs and tooling, the not-so-distant future looks very promising.
Michael is VP Business Development at Antmicro with a background in software and AI. He is chairing the Marketing Content TG of the RISC-V Foundation, of which Antmicro is a Platinum Founding Member. Michael was involved with Renode from the very beginning, working with acquiring users/customers, user experience and documentation, defining use cases and workflows.
An introduction and tutorial on using cocotb and Python to verify your Verilog and VHDL designs. This presentation will cover why you should be using cocotb instead of SystemVerilog and UVM, and its growing usage inside Broadcom, plus an accompanying tutorial on github.
Luke is an ASIC Design Engineer with 14 years experience working in Broadcom's WCC Business designing WLAN and Bluetooth combo chips. He's based in the WLAN ASIC team and has worked on a wide variety of projects including baseband phy implementations, SOC IP integration, ARM-based CPU subsystem design, AXI/AHB/APB backplane designs, block and chip level design verification, radio modeling, silicon implementation, version control and continuous integration.
He became interested in cocotb after a less than compelling experience with UVM and Verilog/SystemVerilog in general. He got Broadcom to sponsor a number of new features and bug fixes. He continues to use cocotb on a daily basis and evangelizes its use inside Broadcom.
Why is functional verification world dominated by UVM? Are UVM users happy with tools and methodology? Does a digital verification really require a digital IC design background? I will try to address modern verification problems and answer why Cocotb-based approach can be a solid alternative to modern flow. I will explain what are the limitations and how Cocotb can be improved to become a comprehensive functional verification platform. Metric-driven verification extensions to Cocotb will be presented as a step towards this goal.
Marek is an experienced digital IC design engineer and PhD specialized in functional verification and digital signal processing. He's implementing extensions for Cocotb to support coverage and randomization. In TDK, he is pushing Cocotb deployment which is very useful for DSP-related tasks.
The cocotb project founders will give us an update on the status of cocotb and what's next.
Chris and Stu have over a decade of experience working with FPGAs in various industries. A software background has shaped their approach to RTL design and verification and they now spend their time trying to bridge the divide between hardware and software development.
The momentum in the RISC-V ecosystem is incredible, with new implementations, ASIC and FPGA improvements and tools cropping up at an impressive pace. With the first RISC-V Summit just around the corner, it's good to get an update on what's been happening and what to expect next.
For the past few months, engineers from Embecosm have been working with SiFive to improve GDB and OpenOCD support for RISC-V. The objective is to provide a clean, reliable debug experience for both single core and multicore systems. This talk will give an update on progress.
Dr Jeremy Bennett is Chief Executive of Embecosm and specializes in processor modeling and debug interfaces.
Andrew Burgess leads Embecosm's GNU tool chain work and is co-maintainer of GDB for RISC-V.
Craig Blackmore has recently joined Embecosm following his PhD research on machine learning and inductive logic programming for compiler optimization.
Quick analysis of the performance, area, and power of the LiteDRAM open source DDR3 controller vs MIG.
John has been working on improving random access performance of LiteDRAM over the last few months. The design at the point now where it is superior to MIG in many cases.
We would like to introduce our Libre Silicon project, who we are, what we are doing and where we are now. While a lot of projects are currently developing their own processors, mostly as open source in Verilog, VHDL or even Chisel, we miss the free process afterwards to manufacture this chips.
The manufacturing is proprietary and has vendor lock-ins with triple NDAs - one for the ""process development kit"" (PDK) , the technology itself; - one for the Standard Cell Library you can use to synthesis your RTL; - and even another one for the details of all purchase commitments.
Our purpose is a free and open, community based silicon manufacturing process (GitHub link) without any NDAs, a Standard Cell Library (GitHub link) not only for that process as well as the a suitable, refurbished, new-written open source tool chain (qtflow).
During the last couple of month we already developed a first 1um process and are now close to manufacturing a first test waver (GitHub link). Well, 1um does not sounds very ambitious, but this process node is still quite well documented in textbooks, robust and 5 Volt-tolerant. Once we got this, the machinery park in the clean room allows us to shrink down to 500nm.
Hagen has been an Open Source enthusiast, freelancer, chip designer since two decades.
ETH Zurich and University of Bologna have been working for the past five years on the PULP project which has resulted in various 32 and 64 bit processing platforms released under a permissive Solderpad license. In this talk, we reflect on both challenges and opportunities we have experienced when dealing with industrial partners for both ASIC and FPGA design flow.
Frank is part of the PULP team from ETH Zurich. He likes to talk, sometimes too much.
~20 years ago Jiri Gaisler released a paper called 'A Structured VHDL Design Method' - which advocates the use of records for storing registers and the use of high-level functions to perform operations on these records. Some years ago I came across this paper and recognized this pattern as object-oriented programming (OOP), which spawned the following question:
Could some higher level OOP language, say Python, be ~directly converted into OOP-VHDL for synthesis? Answer to this question has materialized as Pyha , with some additional features:
Gaspar is the author of Pyha. His interests include Python, VHDL, SDR and comm-cores.
Docker is like a virtual-machine without the speed regression. Install your stuff once and use the resulting image on Linux and CI environments. I’ll demo the dockerization of following components:
Chisel HDL was created to make hardware designers more productive. As a DSL embedded in Scala, it provides designers the full power of functional and objected oriented programming. This has enabled designers to raise the level abstraction and thereby construct powerful, parameterized generators for digital designs.
Chisel was an important step forward, but it is only one piece of the larger puzzle. From using FIRRTL to decouple design from implementation-specific information, to powerful parameterization with Diplomacy, this talk is about pushing the envelope of digital design.
Jack became involved in the Chisel project as a graduate student at UC Berkeley. He is now a software engineer at SiFive and a maintainer of the Chisel3 and FIRRTL projects. His interests include hardware design, simulation, and programming languages.
The presentation will briefly outline the motivation and difficulties behind designing and verifying a flexible, easily configurable RISC-V based processor, while showing how is it possible to solve the problems by using TL-Verilog in design, and also in verification.
WARP-V is a flexible CPU core generator written entirely in TL-Verilog using makerchip.com. It supports RISC-V and custom ISAs and is currently capable of producing designs ranging from a non-pipelined, slow-clock, low-power microcontroller to a high-frequency, seven-stage CPU.
This talk introduces TL-Verilog and WARP-V and then describes the formal verification of WARP-V using riscv-formal, a formal verification framework for RISC-V by Clifford Wolf. Timing-abstraction and transaction-level design are showing significant benefits for hardware modeling, but this is the first demonstration of their benefits for verification modeling. As evidence of these benefits, the verification of all RISC-V configurations of WARP-V is accomplished in a single page of code.
Ákos Hadnagy is a master’s student at TU Delft. He became involved in the WARP-V project through the Google Summer of Code programme this summer. His interest includes heterogenous and reconfigurable computing, FPGA and hardware development.
The Free and Open Source Silicon community is gaining more and more importance and is steadily increasing in size. It'll be time to to sit back for a discussion and think about what we think important issues should be addressed next to take the community to the next level. The session will consist of a brief panel discussion and engage the audience to let us know their thoughts as well.
Verification capability is largely a matter of programming. VHDL is a capable programming language. Like SystemVerilog, writing directly in VHDL is tedious and potentially error prone.Open Source VHDL Verification Methodology (OSVVM) is a methodology and library that simplifies the creation of structured testbenches that are readable and powerful. OSVVM supports the same capabilities that other verification languages (such as SystemVerilog + UVM) support – from a structured testbench framework using transaction level modeling, to functional coverage and randomized test generation, to scoreboards and FIFOs, to error handling utilities, to synchronization utilities, to memory modeling, and to verification components - All you need is OSVVM.
Jim Lewis has 30 plus years of design and teaching experience and is well known within the VHDL community. He is the Chair of the IEEE 1076 VHDL Standards Working Group. He is a co-founder of the Open Source VHDL Verification Methodology (OSVVM) and the chief architect of the packages and methodology. He is an expert VHDL trainer for SynthWorks Design Inc.
In his design practice, he has created designs for print servers, networking, fighter jets, video phones, and space craft.
SCR1 is an open-source MCU-class RISC-V core for deeply embedded applications and accelerator control, developed and maintained by Syntacore. It can be configured for both RV32I and RV32E base instruction sets and also supports optional M and C extensions. SCR1 has been released under permissive Solderpad Hardware License at the 5th RISC-V Workshop and, since then found considerable traction both in the industry and academia. In this session, we provide deep-dive into core features and usage scenarios accumulating about a year of experience supporting it. Our presentation is targeted at advanced users and provides in-depth information about SCR1 usage and bring-up, its configurable features and implementation cost and performance impact.
Ekaterina Berezina is HW Engineer at Syntacore, where she contributes to the SCRx core family development in the RTL designer role. Ekaterina is one of the SCR1 core developers and maintainers. She received her Master’s degree in Computer Science at ITMO University, Saint-Petersburg.
“Quattro S” stands for Security, Safety, Sovereignty and Social Product. The initiative is a group investigating to make the entire IT value chain transparent and secure. The presentation will describe the origin of the group, its objectives and next steps. Specifically:
See the paper "Open Source Value Chains for Addressing Security Issues Efficiently" as an example of some of the initiative's work.
Arnd Weber is a researcher with Karlsruhe Institute of Technology (KIT), Germany. As an economist, he has a track record researching and providing policy advice in the area of IT innovation and security. His most recent work led to the creation of the “Quattro S Initiative”. Partners of the initiative are Fraunhofer Singapore, Fraunhofer SIT, KIT, RheinMain University of Applied Sciences, TU Berlin and Télécom ParisTech.
The Plan 9 operating system was developed at Bell Labs in the 1980s using a new C compiler written by Ken Thompson,which has also been used to implement the kernel of the Inferno OS and to bootstrap early releases of the Go language. Like Plan 9 itself, the compiler is highly portable, elegantly minimalist, lightweight and quick. (The ARM version, for example, is about 21,000 lines of code and compiles itself in seconds on a Raspberry Pi 3.) This talk will describe the recent exercise of re-targeting the Plan 9 C compiler and associated toolchain for the RISC-V instruction set.
Dr Richard Miller learned C in 1977 while porting Dennis Ritchie's original Unix C compiler from the PDP-11 to the Interdata 7/32. Since then he has re-targeted Unix and Plan 9 C compilers for various other CPUs from NS 16032 to Nios II.
Why I did it, very short description of the aspects of Trinity and then how I used 'free' tools to get the job done.
Andre is a digital ASIC designer.