Welcome to the OpenRISC Conference 2014.

The third annual project meeting was held in Munich, Germany over the weekend of Saturday, October 11 and Sunday, October 12 2014.

This is a conference which aims to bring together those involved with open source embedded systems development, from the transistor level up to Linux userspace and beyond.

Photos here, Press: Linux Voice, OptimSoC blog

Conference Location.

The conference was organized by Technische Universität München and located in the university's main area. The conference room is N2128 in building N1. The building is not open on weekends, so that you must enter the university via the main entrance at Arcisstr. 21 (map) and follow the signs.

Conference Schedule.

Friday, October 10

People arriving already on Friday are invited to join us for a dinner at the Paulaner Brauhaus at Kapuzinerplatz. Please send a message to Stefan Wallentowitz as soon as possible so that we can reserve sufficient places.

Saturday, October 11

Sunday, October 12

A playlist of these videos is available here.

Photos of the event are available here, thanks to Philipp Wagner.

Registration.

The conference is free. Please register for the conference nevertheless to ease the planning.

Call For Lightning Talks

There is still the opportunity of applying to give a lightning talk during one of the break intervals throughout the conference weekend. Suitable topics are anything along the lines of computer architecture, digital design, EDA tools and flows, tool chains, debuggers, and software from bare metal RTOS to Linux user space.

Please contact the organisers if you're interested, but we're flexible too and you can approach us during the weekend with your proposal, too.

Presentations and bios

OpenRISC Project Update

The OpenRISC project's annual status report.

mor1kx progress report

The mor1kx core goes from strength to strength, and since we last met, the core's seen a suite of new features improving performance and extending functionality, prominent amongst which is multicore support.

Stefan Kristiansson

Stefan Kristiansson works as an embedded software developer at Espotel Oy, and enjoys spending his free time with everything related to open source CPU design. During his 3.5 years with in the OpenRISC community, he has been involved in practically every area of the project, from developing CPU RTL, such as the the mor1kx OpenRISC implementation, to tool chain ports (LLVM, GCC, binutils) and Linux kernel development.

RISC-V: A Free and Open Instruction Set Architecture

RISC-V is a new instruction set architecture (ISA) that was originally designed to support computer architecture research and education, but for which we now have grander goals: Just as Linux has become the standard OS for most computing devices, we envision RISC-V becoming the standard ISA for all computing devices.

In this talk, I'll first present our arguments why instruction sets want to be free, then introduce our motivations in designing a new ISA, give an overview of the RISC-V ISA, and conclude with current status and future plans.

Krste Asanovic

Krste Asanovic is a Professor in the EECS Department at the University of California, Berkeley. He received a B.A. in Electrical and Information Sciences from Cambridge University in 1987 and a Ph.D. in Computer Science from U.C. Berkeley in 1998. He joined the EECS faculty at MIT in 1998, receiving tenure in 2005. Escaping the brutal Boston winters, he moved back to UC Berkeley and co-founded the Berkeley Parallel Computing Laboratory in 2007. He is currently the Director of the ASPIRE Lab, which includes 11 faculty and around 50 graduate students focused on software and hardware specialization for improved energy efficiency. His various research projects have designed and fabricated over a dozen experimental microprocessor prototypes.

lowRISC

The lowRISC project has been formed to produce a System-on-Chip which will be open source right down to the HDL, implementing the open RISC-V instruction set architecture. We plan volume silicon manufacture and will be creating and distributing low-cost development boards. This talk will describe the aims of the lowRISC project, summarise its current status, describe some of the features we are implementing, and give details on how you can get involved.

Alex Bradbury

Alex Bradbury (@asbradbury) is a co-founder of the lowRISC project. He is a researcher at the University of Cambridge Computer Laboratory where he works on compilation techniques for a novel many-core architecture. Additionally, he writes LLVM Weekly (@llvmweekly), is co-author of Learning Python with Raspberry Pi, and has been a contributor to the Raspberry Pi project since the first alpha hardware was available.

SDB: Self Describing Bus

SDB is a data structure, to be stored on ROM-alike memory, that describes an address space made of cores. Each core has a vendor ID, a device ID, name and other attributes. We require 64 bytes of storage to describe each code, within a 64-bit address space, plus one extra 64 bytes for each interconnect. Informational structures are available to easy design-wide identification, including web links and commit identifiers.

We also use SDB for information storage in small EEPROM devices. This is a great step forward over using hardwired addresses, as we can now make sense of eeprom images in various environment. The same library functions we use to enumerate cores (either in the soft-cpu within the fpga itself or in the host operating system) can also be used to access stored configuration data, so the code overhead is very limited. Like an address space, an SDB storage device has a read-only structure but can include read-write files; to this aim SDB aligns all writable files to the erase blocks of the host flash/eeprom device.

The presentation will show the design ideas behind SDB, our use for FPGA address spaces and storage, and the software support we provide to users of SDB.

Open Source Licensing

A status report on the state of open source licensing for hardware and digital designs. Alessandro works with CERN who publish the CERN OHL, and who are actively promoting the development and use of open source hardware in general. More recently, discussions have gone to licensing of HDL designs(1, 2), a topic which is fraught with uncertainties about exactly what rights may be afforded the author in the event of it being used in a simulation, an FPGA bistream, or a manufactured ASIC.

Alessandro Rubini

Alessandro is working on SDB as consultant for the hardware and timing section of the CERN controls group. SDB is designed jointly by CERN and GSI within the White Rabbit project. The specification, HDL macros, and software are published with a Free License on ohwr.org, in the fpga-config-space project.

PULP: OpenRISC-based ultra-low power parallel platform

PULP is a parallel, low-power architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability. The PULP platform targets a number of high-growth application areas such as Internet of Things, e-health, wearable human-computer interfaces.

The PULP project currently involves several universities and research centers in Europe including University of Bologna, Swiss Federal Institute of Technology Zurich (ETHZ), Politecnico di Milano, Swiss Federal Institute of Technology in Lausanne (EPFL), and Laboratory for Electronics and Information Technolog­y of Atomic Energy and Alternative Energies Commission (CEA-LETI). This talk will describe the aims of the PULP project, and summarize its current status and plans for future evolutions of the project.

Davide Rossi

Davide Rossi received the M.Sc. degree from the University of Bologna, in 2007, and the Ph.D. degree from the University of Bologna, in 2012, all in electronics engineering. He has been a Consultant with STMicroelectronics since 2008, where he is involved in reconfigurable architectures. He is currently post doctoral fellow at University of Bologna where he works on low-power, energy-efficienct many-core architectures.

Exploration of an extended OpenRISC processor supported by a LLVM-based compiler

This talk will present the joint work of Politecnico di Milano, Swiss Federal Institute of Technology Zurich (ETHZ) and University of Bologna for extending the ISA of the OR1000 processor. We implemented, both in the hardware and in the compiler, two sets of new instructions: 1) hardware loops 2) additional addressing modes for load/store instructions.

Michele Beretta

Michele Beretta received his B.Sc. and M.Sc. in Computer Science Engineering from Politecnico di Milano in 2011 and 2013. He is now a research assistant at DEIB (Department of Electronics Information and Bioengineering) working on the development of an LLVM backend for the OpenRISC processor.

migen and miSoC

Migen is a powerful open source Python framework for writing digital designs (ASIC/FPGA): it allows the design logic to be generated by a Python program which enables hardware designers to take advantage of the richness of the Python language - object oriented programming, function parameters, generators, operator overloading, libraries, etc. - to build well organized, reusable and elegant designs.

MiSoC is a complete open source System-on-Chip designed entirely with Migen. It works across many different boards and FPGA vendors, letting you chose LatticeMico32 or mor1kx as CPU with a simple command line switch.

This presentation will show what Migen looks like, what it can do and how to very easily start using it, in the form of a terminal based demo.

Yann Sionneau

Yann Sionneau is a 26 year old Embedded software engineer working at M-Labs on open source software and FPGA design using Migen technology. Since he touched his first computer he has always been driven by his curiosity to try and understand the underlying technology, digging deeper and deeper in the computer architecture layers. This curiosity then turned into the passion of learning from and playing with (deeply) embedded architectures, down to how System-on-Chips and CPUs actually work.

Within the M-Labs (formerly known as Milkymist) community, he wrote the basic parts of the Board Support Package (of RTEMS) running on the Milkymist One digital video synthesizer. He then participated (with Michael Walle) in the design of an MMU for the LatticeMico32 CPU and then ported the NetBSD 6 kernel to run on the Milkymist SoC.

Contact

Feel free to contact the event organisers with any questions or comments about the weekend

The OpenRISC project's mailing lists and IRC room are also useful points of contact for anything regarding the weekend

IRC: #openrisc on irc.freenode.net.

Travel and Stay.

Munich is the third largest city in Germany and can be easily reached by airplane (MUC) or by train (train operator). There is a second airport (FMM) used by Ryanair, which is imprecisely referred to as "Munich West". The actual distance is about 120 km from Munich, so please consider this in your travel plans.

A variety of hotels and hostels are available all over the city.

For budget travel, there are a few hostels such as Wombat's, A&O, Jaeger's, Euro Youth Hotel and many others

Especially south of the main train station (along Schillerstr. and Schwanthalerstr.) there are many budget to midcost hotels available: Hotel Stachus, Hotel Condor, Hotel Metropol, Hotel Helvetia, Schiller 5, Hotel 3 Löwen, Conrad Hotel, Hotel Ambiente, Pension am Hauptbahnhof, Hotel Cocoon, Hotel Royal, Hotel Präsident, Alpenhotel München, Hotel Germania, Hotel Marc, Leonardo Hotel, Hotel Dolomit, Hotel Goethe, just to name a few.

All over the city you can find standard class chain hotels: NH Hotels, Mercure, Best Western Hotel Cristal, Motel One, Novotel, Holiday Inn.

Of course this is just a selection. Please refer to the usual suspects to find your hotel: Tripadvisor, booking.com, HRS, etc.

Previous Editions.

2013, 2012

Sponsors.